Design and FPGA Implementation of High Speed Vedic Multiplier

International Journal of Computer Applications ◽

10.5120/15802-4641 ◽

2014 ◽

Vol 90 (16) ◽

pp. 6-9 ◽

Author(s):

Sudeep. M.C ◽

Sharath Bimba.M ◽

Mahendra Vucha

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier

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FPGA implementation of high speed Vedic multiplier

International Conference & Workshop on Electronics & Telecommunication Engineering (ICWET 2016) ◽

10.1049/cp.2016.1144 ◽

2016 ◽

Author(s):

S.N. Gadakh ◽

A.S. Khade

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier

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FPGA implementation of high speed 8-bit Vedic multiplier using barrel shifter

2013 International Conference on Energy Efficient Technologies for Sustainability ◽

10.1109/iceets.2013.6533349 ◽

2013 ◽

Author(s):

U. C. S. P. Kumar ◽

A. S. Goud ◽

A. Radhika

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier ◽

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FPGA implementation of high speed Vedic multiplier using CSLA for parallel FIR architecture

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcsyst.2014.6926136 ◽

2014 ◽

Author(s):

S. Amina Naaz ◽

M. N. Pradeep ◽

Satish Bhairannawar ◽

Srinivas Halvi

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier

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FPGA Implementation of Simple and High Speed Vedic Multiplier

International Journal of VLSI & Signal Processing ◽

10.14445/23942584/ijvsp-v2i2p102 ◽

2015 ◽

Vol 2 (2) ◽

pp. 6-9

Author(s):

Shilpi Thawait ◽

Jagveer Verma

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier

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VLSI design of high speed Vedic Multiplier for FPGA implementation

2016 IEEE International Conference on Engineering and Technology (ICETECH) ◽

10.1109/icetech.2016.7569385 ◽

2016 ◽

Author(s):

Kapil Ram Gavali ◽

Poonam Kadam

Keyword(s):

Vlsi Design ◽

Fpga Implementation ◽

Vedic Multiplier

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FPGA implementation of high speed 8 bit Vedic Multiplier using Fast adders

IOSR Journal of VLSI and Signal processing ◽

10.9790/4200-04325459 ◽

2014 ◽

Vol 4 (3) ◽

pp. 54-59

Author(s):

Mrs.Toni J.Billore ◽

◽

Prof.D.R. Rotake

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier

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FPGA Implementation of Novel High Speed Vedic Multiplier

International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering ◽

10.15662/ijareeie.2015.0406046 ◽

2015 ◽

Vol 04 (06) ◽

pp. 5571-5577

Author(s):

Amruta Ingle, Dr. Shruti Oza

Keyword(s):

Fpga Implementation ◽

Vedic Multiplier

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FPGA Implementation of Low Power and High Speed Vedic Multiplier using Vedic Mathematics.

IOSR Journal of VLSI and Signal processing ◽

10.9790/4200-0255157 ◽

2013 ◽

Vol 2 (5) ◽

pp. 51-57 ◽

Author(s):

Keyword(s):

Low Power ◽

Fpga Implementation ◽

Vedic Mathematics ◽

Vedic Multiplier

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Design, FPGA implementation and statistical analysis of a high-speed and low-area TRNG based on an AES s-box post-processing technique

ISA Transactions ◽

10.1016/j.isatra.2021.01.054 ◽

2021 ◽

Author(s):

Ali Murat Gari̇pcan ◽

Ebubekir Erdem

Keyword(s):

Statistical Analysis ◽

Processing Technique ◽

Fpga Implementation ◽

Post Processing ◽

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FPGA Implementation and Study of Synchronization of Modified Chua’s Circuit-Based Chaotic Oscillator for High-Speed Secure Communications

2020 IEEE 8th Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE) ◽

10.1109/aieee51419.2021.9435783 ◽

2021 ◽

Author(s):

Filips Capligins ◽

Anna Litvinenko ◽

Arturs Aboltins ◽

Deniss Kolosovs

Keyword(s):

Fpga Implementation ◽

Chaotic Oscillator ◽

Secure Communications ◽

Chua’S Circuit ◽

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