A Statement Level Bug Localization Technique using Statement Dependency Graph

Software development teams that use agile methodologies are increasingly adopting the test-driven development practice (TDD). TDD allows to produce software by iterative and incremental work cycle, and with a strict control over the process, favouring an early detection of bugs. However, when applied to large and complex systems, TDD benefits are not so obvious; manually locating and fixing bugs introduced during the iterative development steps is a nontrivial task. In such systems, the propagation chains following the bugs activation can be unacceptably long and intricate, and the size of the code to be analyzed is often too large. In this paper, a bug localization technique specifically tailored to TDD is presented. The technique is embedded in the TDD cycle, and it aims to improve developers' ability to locate bugs as soon as possible. It is implemented in a tool and experimentally evaluated on newly developed Java programs.

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dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2013p0255 ◽

2013 ◽

Author(s):

Sweta Pendyala ◽

Dave Albert ◽

Katherine Hawkins ◽

Michael Tenney

Keyword(s):

Deep Submicron ◽

Work Flow ◽

Localization Technique ◽

Characterization Techniques ◽

Capacitance Voltage ◽

Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

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FINAL VERSION.pdf

10.36227/techrxiv.10252637.v1 ◽

2019 ◽

Author(s):

Nasir Saeed ◽

Mohamed-Slim Alouini ◽

Tareq Y. Al-Naffouri

Keyword(s):

Graph Partitioning ◽

Three Dimensional ◽

Smart Objects ◽

Localization Technique ◽

Optical Internet ◽

Spectral Graph ◽

Accurate Localization ◽

Spectral Graph Partitioning ◽

Link Connectivity

<div>Localization is a fundamental task for optical internet</div><div>of underwater things (O-IoUT) to enable various applications</div><div>such as data tagging, routing, navigation, and maintaining link connectivity. The accuracy of the localization techniques for OIoUT greatly relies on the location of the anchors. Therefore, recently localization techniques for O-IoUT which optimize the anchor’s location are proposed. However, optimization of anchors location for all the smart objects in the network is not a useful solution. Indeed, in a network of densely populated smart objects, the data collected by some sensors are more valuable than the data collected from other sensors. Therefore, in this paper, we propose a three-dimensional accurate localization technique by optimizing the anchor’s location for a set of smart objects. Spectral graph partitioning is used to select the set of valuable</div><div>sensors.</div>

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