Direct Plan View FIB Liftout for Near-Surface Defect Analysis in TEM

Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.

A New Deprocess Flow of Failure Analysis for MEMS Motion Sensor

This paper demonstrates a new de-process flow for MEMS motion sensor failure analysis, using layer by layer deprocessing to locate defect points. Analysis tools used in this new process flow include IR optical microscopy, thermal system, SEM and a cutting system to de-process of MEMS motion sensor and successful observation defect points.

Silicon Fringe Sample Metrology—A Thickness Measurement Technique

Silicon’s index of refraction has a strong temperature coefficient. This temperature dependence can be used to aid sample thinning procedures used for backside analysis, by providing a noncontact method of measuring absolute sample thickness. It also can remove slope ambiguity while counting interference fringes (used to determine the direction and magnitude of thickness variations across a sample).

Validity-Study of Commercial Semiconductor with TO-18 Package for Space Application by PIND Test

In this paper, we carried out PIND (Particle Impact Noise Detection) test and X-ray inspection of a transistor in a TO-18 package for commercial and industrial applications. From our evaluation results, we explain the validity of the PIND test by comparing PIND test and X-ray inspection results. We make clear that PIND test is able to detect internal foreign material that may be transparent to X-ray inspection. In addition, we report analysis results of internal foreign materials from defective devices. This matter suggests that a problem is contamination control in the manufacturing process, most likely the sealing process.

Rapid Failure Analysis of Low-Yielding Electrical Test Structures Using E-beam Physical and Voltage Contrast Inspection

In-line E-beam inspection may be used for rapid generation of failure analysis (FA) results for low yielding test structures. This approach provides a number of advantages: 1) It is much earlier than traditional FA, 2) de-processing isn’t required, and 3) a high volume of sites can be processed with the additional support of an in-line FIB. Both physical defect detection and voltage contrast inspection modes are useful for this application. Voltage contrast mode is necessary for isolation of buried defects and is the preferred approach for opens, because it is faster. Physical defect detection mode is generally necessary to locate shorts. The considerations in applying these inspection modes for rapid failure analysis are discussed in the context of two examples: one that lends itself to physical defect inspection and the other, more appropriately addressed with voltage contrast inspection.

Localization of a Complex Failure by Combining ATPG and Customer-Oriented Application Testing

A systemic analysis was chosen to evaluate a real case Bluetooth (BT) radio failure in the aspects of RF communication, digital design, firmware, application software, semiconductor device physics and processing, and failure analysis. This paper explores the range of testing, including customer application testing, required to confirm and localize a BT RF communication failure. It shows that the radio communication failure was not, as expected, caused by faulty radio hardware; it was rather linked to problematic encryption hardware at the assistance of the Synergy BT to mobile application. The paper also explores that the digital fault can only be detected by the timing sensitive transition fault scan patterns and how to obtain the physical failure location. Thus, the combination of ATPG and application testing provides a consistency between electrical diagnostics which yields a higher success rate at subsequent physical failure analysis of complex modern RF System on a Chip.

Data Center Equipment Reliability Concerns—Contamination Issues, Standards Actions, and Case Studies

Lead-free manufacturing regulations, reduction in circuit board feature sizes and the miniaturization of components to improve hardware performance have combined to make data center IT equipment more prone to attack by corrosive contaminants. Manufacturers are under pressure to control contamination in the data center environment and maintaining acceptable limits is now critical to the continued reliable operation of datacom and IT equipment. This paper will discuss ongoing reliability issues with electronic equipment in data centers and will present updates on ongoing contamination concerns, standards activities, and case studies from several different locations illustrating the successful application of contamination assessment, control, and monitoring programs to eliminate electronic equipment failures.

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

Failure Analysis Due to Slightly Unetched Hard Mask Using Nano Probe

In this work, a slightly unetched gate hard mask failure was analyzed by nano probing. Although unetched hard mask failures are commonly detected from the cross sectional view with FIB or FIB-TEM and planar view with the voltage contrast, in this case of the very slightly unetched hard mask, it was difficult to find the defects within the failed area by physical analysis methods. FIB is useful due to its function of milling and checking from the one region to another region within the suspected area, but the defect, located under contact was very tiny. So, it could not be detected in the tilted-view of the FIB. However, the state of the failure could be understood from the electrical analysis using a nano probe due to its ability to probe contact nodes across the fail area. Among the transistors in the fail area, one transistor’s characteristics showed higher leakage current and lower ON current than expected. After physical analysis, slightly remained hard mask was detected by TEM. Chemical processing was followed to determine the gate electrode (WSi2) connection to tungsten contact. It was also proven that when gate is floated, more leakage current flows compared to the state that the zero voltage is applied to the gate. This was not verified by circuit simulation due to the floating nodes.

A Study of Electron Beam Irradiation Influence on Device Contact Junction Characteristics of Advanced DRAM Using Atomic Force Probing

In this paper, we revealed p+/n-well and n+/p-well junction characteristic changes caused by electron beam (EB) irradiation. Most importantly, we found a device contact side junction characteristic is relatively sensitive to EB irradiation than its whole device characteristic; an order of magnitude excess current appears at low forward bias region after 1kV EB acceleration voltage irradiation (Vacc). Furthermore, these changes were well interpreted by our Monte Carlo simulation results, the Shockley-Read Hall (SRH) model and the Generation-Recombination (G-R) center trap theory. In addition, four essential examining items were suggested and proposed for EB irradiation damage origins investigation and evaluation. Finally, by taking advantage of the excess current phenomenon, a scanning electron microscope (SEM) passive voltage contrast (PVC) fault localization application at n-FET region was also demonstrated.