dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

Construction of plastic contact deformation maps on ceramics: a case study on aluminum nitride

1996 ◽  
Vol 54 ◽  
pp. 636-637
Author(s):  
D. L. Callahan
Keyword(s):  
Plastic Deformation ◽  
Aluminum Nitride ◽  
Mechanical Response ◽  
Three Dimensional ◽  
Bright Field Image ◽  
Perfectly Plastic ◽  
Contrast Analysis ◽  
Deformation Patterns

Modern polishing, precision machining and microindentation techniques allow the processing and mechanical characterization of ceramics at nanometric scales and within entirely plastic deformation regimes. The mechanical response of most ceramics to such highly constrained contact is not predictable from macroscopic properties and the microstructural deformation patterns have proven difficult to characterize by the application of any individual technique. In this study, TEM techniques of contrast analysis and CBED are combined with stereographic analysis to construct a three-dimensional microstructure deformation map of the surface of a perfectly plastic microindentation on macroscopically brittle aluminum nitride.The bright field image in Figure 1 shows a lg Vickers microindentation contained within a single AlN grain far from any boundaries. High densities of dislocations are evident, particularly near facet edges but are not individually resolvable. The prominent bend contours also indicate the severity of plastic deformation. Figure 2 is a selected area diffraction pattern covering the entire indentation area.

Integrating The Geophysical Characterization Of Seismic Thin Beds With Stochastic Reservoir Modeling: A Case Study From The Kutei Basin (Offshore Kalimantan, Indonesia)

2011 ◽  
Author(s):  
Giorgio Rocco Cavanna ◽  
Ernesto Caselgrandi ◽  
Elisa Corti ◽  
Alessandro Amato del Monte ◽  
Massimo Fervari ◽  
...  
Keyword(s):  
Reservoir Modeling ◽  
Geophysical Characterization

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

Nanoprobe Characterization of Soft SRAM bit Fails in Advanced Technologies

2019 ◽  
Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh
Keyword(s):  
Yield Loss ◽  
Performance Metrics ◽  
Root Cause ◽  
Advanced Technologies ◽  
Capacitance Voltage ◽  
Defect Localization ◽  
Cv Measurements ◽  
Lightly Doped Drain ◽  
Dc Characterization

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices

2007 ◽  
Author(s):  
Martin Versen ◽  
Dorina Diaconescu ◽  
Jerome Touzel
Keyword(s):  
Failure Mode ◽  
Failure Modes ◽  
Fault Modeling ◽  
Mode Analysis ◽  
Root Cause ◽  
Failure Mode Analysis

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

Thermal Frequency Imaging: A New Application of Laser Voltage Imaging Applied on 40nm Technology

2011 ◽  
Author(s):  
Guillaume Celi ◽  
Sylvain Dudit ◽  
Thierry Parrassin ◽  
Philippe Perdu ◽  
Antoine Reverdy ◽  
...  
Keyword(s):  
Charge Carrier ◽  
Laser Beam ◽  
Integrated Circuit ◽  
Carrier Density ◽  
Deep Submicron ◽  
Charge Carrier Density ◽  
Voltage Imaging ◽  
A New Technique ◽  
Scan Chain

Abstract For Very Deep submicron Technologies, techniques based on the analysis of reflected laser beam properties are widely used. The Laser Voltage Imaging (LVI) technique, introduced in 2009, allows mapping frequencies through the backside of integrated circuit. In this paper, we propose a new technique based on the LVI technique to debug a scan chain related issue. We describe the method to use LVI, usually dedicated to frequency mapping of digital active parts, in a way that enables localization of resistive leakage. Origin of this signal is investigated on a 40nm case study. This signal can be properly understood when two different effects, charge carrier density variations (LVI) and thermo reflectance effect (Thermal Frequency Imaging, TFI), are taken into account.

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