scholarly journals A Novel De Bruijn Based Mesh Topology for Networks-on-Chip

VLSI ◽  
10.5772/8254 ◽  
2010 ◽  
Author(s):  
Reza Sabbaghi-Nadooshan ◽  
Mehdi Modarressi ◽  
Hamid Sarbazi-Az
Keyword(s):  
Networks On Chip ◽  
Mesh Topology ◽  
De Bruijn ◽  
On Chip

scholarly journals Level Based Routing Using Dynamic Programming for 2D Mesh

2017 ◽  
Vol 17 (2) ◽  
pp. 73-82 ◽  
Author(s):  
Akash Punhani ◽  
Pardeep Kumar ◽  
Nitin Nitin
Keyword(s):  
Dynamic Programming ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Networks On Chip ◽  
Mesh Topology ◽  
On Chip

Abstract The performance of the interconnection network doesn’t only depend on the topology, but it also depends on the Routing algorithm used. The simplest Routing algorithm for the mesh topology in networks on chip is the XY Routing algorithm. The level based Routing algorithm has been proved to be more efficient than the XY Routing algorithm. In this paper, level based Routing algorithm using the dynamic programming has been proposed. The proposed Routing algorithm proves to be more efficient in the terms of the computation. The proposed Routing algorithm has achieved up to two times bigger speed.

Efficient and scalable cross‐by‐pass‐mesh topology for networks‐on‐chip

2017 ◽  
Vol 11 (4) ◽  
pp. 140-148 ◽  
Author(s):  
Usman Ali Gulzari ◽  
Sheraz Anjum ◽  
Shahrukh Aghaa ◽  
Sarzamin Khan ◽  
Frank Sill Torres
Keyword(s):  
Networks On Chip ◽  
Mesh Topology ◽  
On Chip

scholarly journals Shuffle-Exchange Mesh Topology for Networks-on-Chip

10.5772/9445 ◽  
2010 ◽  
Author(s):  
Reza Sabbaghi-Nadooshan ◽  
Mehdi Modarressi ◽  
Hamid Sarbazi-Az
Keyword(s):  
Networks On Chip ◽  
Mesh Topology ◽  
On Chip

AN ANALYTICAL COMPARISON OF THE SPIDERGON AND RECTANGULAR MESH NoCs

2009 ◽  
Vol 10 (01n02) ◽  
pp. 167-188
Author(s):  
MAHMOUD MOADELI ◽  
ALI SHAHRABI ◽  
WIM VANDERBAUWHEDE ◽  
MOHAMED OULD-KHAOUA
Keyword(s):  
Discrete Event ◽  
Cost Effective ◽  
Network Throughput ◽  
Analytical Models ◽  
Networks On Chip ◽  
Mesh Topology ◽  
Systems On Chip ◽  
Rectangular Mesh ◽  
On Chip ◽  
Scalable Communication

Networks on chip (NoC) emerged as a structured and scalable communication medium for development of future Systems-on-Chip (SoC). Due to its unique features in terms of scalability and ease of synthesis, the (rectangular) mesh topology is regarded as an appropriate candidate for on-chip network development. On the other hand, the Spidergon NoC has been proposed as an alternative topology to realize cost effective multi-processor SoC (MPSoC) development. This paper presents analytical models of the average message latency and network throughput for both rectangular mesh and the Spidergon NoC employing wormhole switching. For each model, the validity of the analysis is verified by comparing the analytical model against the results produced by a discrete event simulator. Using the developed models, we then compare these topologies from different perspectives including manufacturing issues, message latency and network throughput.

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip

scholarly journals Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications

2018 ◽  
Vol 8 (4) ◽  
pp. 39 ◽  
Author(s):  
Franco Fuschini ◽  
Marina Barbiroli ◽  
Marco Zoli ◽  
Gaetano Bellanca ◽  
Giovanna Calò ◽  
...  
Keyword(s):  
Ray Tracing ◽  
Path Loss ◽  
Wireless Channel ◽  
Electromagnetic Propagation ◽  
Networks On Chip ◽  
Spatial Properties ◽  
Radiation Properties ◽  
Wireless Optical Communications ◽  
On Chip ◽  
The Relationship

Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties.

Deadlock-Free Adaptive Routing in Networks -on-Chip Using Overlapping Virtual Networks

2021 ◽  
pp. 1-1
Author(s):  
Dong Xiang ◽  
Xiang Ji ◽  
Yuan Cai ◽  
Binzhang Fu
Keyword(s):  
Adaptive Routing ◽  
Virtual Networks ◽  
Networks On Chip ◽  
On Chip

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

Predicting Networks-on-Chip traffic congestion with Spiking Neural Networks

2021 ◽  
Author(s):  
Aqib Javed ◽  
Jim Harkin ◽  
Liam McDaid ◽  
Junxiu Liu
Keyword(s):  
Neural Networks ◽  
Traffic Congestion ◽  
Spiking Neural Networks ◽  
Networks On Chip ◽  
On Chip

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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