AN ANALYTICAL COMPARISON OF THE SPIDERGON AND RECTANGULAR MESH NoCs

Networks on chip (NoC) emerged as a structured and scalable communication medium for development of future Systems-on-Chip (SoC). Due to its unique features in terms of scalability and ease of synthesis, the (rectangular) mesh topology is regarded as an appropriate candidate for on-chip network development. On the other hand, the Spidergon NoC has been proposed as an alternative topology to realize cost effective multi-processor SoC (MPSoC) development. This paper presents analytical models of the average message latency and network throughput for both rectangular mesh and the Spidergon NoC employing wormhole switching. For each model, the validity of the analysis is verified by comparing the analytical model against the results produced by a discrete event simulator. Using the developed models, we then compare these topologies from different perspectives including manufacturing issues, message latency and network throughput.

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Modeling and Simulation of Network-on-Chip Systems with DEVS and DEUS

The Scientific World JOURNAL ◽

10.1155/2014/982569 ◽

2014 ◽

Vol 2014 ◽

pp. 1-9 ◽

Cited By ~ 2

Author(s):

Michele Amoretti

Keyword(s):

Modeling And Simulation ◽

Discrete Event ◽

General Purpose ◽

System Specification ◽

Modeling Framework ◽

Steep Learning Curve ◽

Networks On Chip ◽

Systems On Chip ◽

Communication Architectures ◽

On Chip

Networks on-chip (NoCs) provide enhanced performance, scalability, modularity, and design productivity as compared with previous communication architectures for VLSI systems on-chip (SoCs), such as buses and dedicated signal wires. Since the NoC design space is very large and high dimensional, evaluation methodologies rely heavily on analytical modeling and simulation. Unfortunately, there is no standard modeling framework. In this paper we illustrate how to design and evaluate NoCs by integrating the Discrete Event System Specification (DEVS) modeling framework and the simulation environment called DEUS. The advantage of such an approach is that both DEVS and DEUS support modularity—the former being a sound and complete modeling framework and the latter being an open, general-purpose platform, characterized by a steep learning curve and the possibility to simulate any system at any level of detail.

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Delta Multi-Stage Interconnection Networks for Scalable Wireless On-Chip Communication

Electronics ◽

10.3390/electronics9060913 ◽

2020 ◽

Vol 9 (6) ◽

pp. 913 ◽

Cited By ~ 3

Author(s):

Sirine Mnejja ◽

Yassine Aydi ◽

Mohamed Abid ◽

Salvatore Monteleone ◽

Vincenzo Catania ◽

...

Keyword(s):

Interconnection Networks ◽

Interconnection Network ◽

Average Delay ◽

Networks On Chip ◽

Energy Profiles ◽

Multi Stage ◽

Systems On Chip ◽

Viable Solution ◽

On Chip ◽

Scalable Communication

The Network-on-Chip (NoC) paradigm emerged as a viable solution to provide an efficient and scalable communication backbone for next-generation Multiprocessor Systems-on-Chip. As the number of integrated cores keeps growing, alternatives to the traditional multi-hop wired NoCs, such as wireless Networks-on-Chip (WiNoCs), have been proposed to provide long-range communications in a single hop. In this work, we propose and analyze the integration of the Delta Multistage Interconnection Network (MINs) as a backbone for wireless-enabled NoCs. After extending the well-known Noxim platform to implement a cycle-accurate model of a wireless Delta MIN, we perform a comprehensive set of SystemC simulations to analyze how wireless-augmented Delta MINs can potentially lead to an improvement in both average delay and saturation. Further, we compare the results obtained with traditional mesh-based topologies, reporting energy profiles that show an overall energy cost reduced on both wired/wireless scenarios.

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A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽

10.3390/mi12020183 ◽

2021 ◽

Vol 12 (2) ◽

pp. 183

Author(s):

Jose Ricardo Gomez-Rodriguez ◽

Remberto Sandoval-Arechiga ◽

Salvador Ibarra-Delgado ◽

Viktor Ivan Rodriguez-Abdala ◽

Jose Luis Vazquez-Avila ◽

...

Keyword(s):

Single Chip ◽

Synthesis Time ◽

Networks On Chip ◽

Data Dependencies ◽

Layered Architecture ◽

Systems On Chip ◽

Challenges And Opportunities ◽

Computing Platforms ◽

On Chip ◽

Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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Diseño e Implementación de un Multiprocessor Systems-on-Chip (MPSoC) Interconectado por una Networks-on-Chip (NoC)

MASKAY ◽

10.24133/maskay.v3i1.129 ◽

2013 ◽

Vol 3 (1) ◽

pp. 40

Author(s):

Wilson Mauricio Chicaiza ◽

Daniel Gonzalo Verdesoto

Keyword(s):

Multiprocessor Systems ◽

Networks On Chip ◽

Systems On Chip ◽

On Chip ◽

Medios De Comunicacion

En el presente documento se presenta una breve caracterización de los medios de comunicación empleados en arquitecturas multiprocesadas. Esta caracterización tiene como objetivo principal el mostrar un nuevo modelo de comunicación basado en conmutación de paquetes a los cuales se les denomina como Networks-On-Chip (NoC). Esta publicación muestra una arquitectura de red llamada NoC Hermes, la cual fue interconectada a un Multiprocessor-Systems-on-Chip (MPSoC) compuesto de cuatro procesadores MicroBlaze. Está conexión se la realizó gracias al diseño y desarrollo de una Interfaz de Red generada en código VHDL. Por medio de la Interfaz de Red se consiguió que los procesadores MicroBlaze interactúen con los Switches de Hermes a fin de crear una arquitectura multiprocesada interconectada por una NoC. Con el motivo de realizar comparaciones también se creó otra arquitectura de multiprocesadores interconectados por buses. Para ambas arquitecturas se desarrolló una aplicación de Esteganografía enla que existe multiprocesamiento de dos procesadores trabajando simultáneamente. Lamentablemente sobre dicha aplicación no fue posible medir directamente la latencia y el consumo de energía, razón por la cual se utilizó simuladores que permitieron estimar dichas mediciones.

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Level Based Routing Using Dynamic Programming for 2D Mesh

Cybernetics and Information Technologies ◽

10.1515/cait-2017-0017 ◽

2017 ◽

Vol 17 (2) ◽

pp. 73-82 ◽

Cited By ~ 3

Author(s):

Akash Punhani ◽

Pardeep Kumar ◽

Nitin Nitin

Keyword(s):

Dynamic Programming ◽

Interconnection Network ◽

Routing Algorithm ◽

Networks On Chip ◽

Mesh Topology ◽

On Chip

Abstract The performance of the interconnection network doesn’t only depend on the topology, but it also depends on the Routing algorithm used. The simplest Routing algorithm for the mesh topology in networks on chip is the XY Routing algorithm. The level based Routing algorithm has been proved to be more efficient than the XY Routing algorithm. In this paper, level based Routing algorithm using the dynamic programming has been proposed. The proposed Routing algorithm proves to be more efficient in the terms of the computation. The proposed Routing algorithm has achieved up to two times bigger speed.

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3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306588 ◽

2009 ◽

Cited By ~ 20

Author(s):

Yaoyao Ye ◽

Lian Duan ◽

Jiang Xu ◽

Jin Ouyang ◽

Mo Kwai Hung ◽

...

Keyword(s):

Optical Networks ◽

Multiprocessor Systems ◽

Networks On Chip ◽

Systems On Chip ◽

On Chip

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Wearout and Variation Tolerant Source Synchronous Communication for GALS Network-on-Chip Design

Advances in Systems Analysis, Software Engineering, and High Performance Computing - Advancing Embedded Systems and Real-Time Communications with Emerging Technologies ◽

10.4018/978-1-4666-6034-2.ch016 ◽

2014 ◽

pp. 399-419

Author(s):

Alessandro Strano ◽

Carles Hernández ◽

Federico Silla ◽

Davide Bertozzi

Keyword(s):

Cost Effective ◽

Internal Communication ◽

Synchronous Communication ◽

Chip Design ◽

Networks On Chip ◽

Switch Architecture ◽

Network Operation ◽

Placement And Routing ◽

Delay Variations ◽

On Chip

In the context of multi-IP chips making use of internal communication paths other than the traditional buses, source synchronous links for use in multi-synchronous Networks-on-Chip (NoCs) are becoming the most vulnerable points for correct network operation and therefore need to be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies, as well as the deterioration due to the ageing of the chip, are the root causes for this. This chapter addresses the challenge of designing a timing variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A timing variation detector senses the misalignment, due to process variation and wearout, between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. This chapter proves the robustness of the link in isolation with respect to a detector-less link, also addressing integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

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Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

Dynamic Reconfigurable Network-on-Chip Design ◽

10.4018/978-1-61520-807-4.ch002 ◽

2010 ◽

pp. 28-66 ◽

Cited By ~ 1

Author(s):

Mário P. Véstias ◽

Horácio C. Neto

Keyword(s):

Quality Of Service ◽

Power Consumption ◽

First Generation ◽

Networks On Chip ◽

Dynamically Reconfigurable ◽

Systems On Chip ◽

High Bandwidth ◽

Area Occupation ◽

On Chip

The recent advances in IC technology have made it possible to implement systems with dozens or even hundreds of cores in a single chip. With such a large number of cores communicating with each other there is a strong pressure over the communication infrastructure to deliver high bandwidth, low latency, low power consumption and quality of service to guarantee real-time functionality. Networks-on-Chip are definitely becoming the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC). The first generation of NoC solutions considers a regular topology, typically a 2D mesh. Routers and network interfaces are mainly homogeneous so that they can be easily scaled up and modular design is facilitated. All advantages of a NoC infrastructure were proved with this first generation of NoC solutions. However, NoCs have a relative area and speed overhead. Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed with improved area. The efficiency of both homogeneous and heterogeneous solutions can be improved if runtime changes are considered. Dynamically or runtime reconfigurable NoCs are the second generation of NoCs since they represent a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance and quality of service compared to the previous generation where the architecture is decided at design time. This chapter discusses the static and runtime customization of routers and presents results with networks-on-chip with static and adaptive routers. Runtime adaptive techniques are analyzed and compared to each other in terms of area occupation and performance. The results and the discussion presented in this chapter show that dynamically adaptive routers are fundamental in the design of NoCs to satisfy the requirements of today’s systems-on-chip.

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