scholarly journals An Efficient Hardware Implementation of Lightweight Block Cipher LEA-128/192/256 for IoT Security Applications

2015 ◽  
Vol 19 (7) ◽  
pp. 1608-1616 ◽  
Author(s):  
Mi-Ji Sung ◽  
Kyung-Wook Shin
Keyword(s):  
Hardware Implementation ◽  
Block Cipher ◽  
Iot Security ◽  
Security Applications ◽  
Lightweight Block Cipher

scholarly journals Complexity analysis and hardware implementation of extensible modulo addition for lightweight block cipher in Internet of Things (IOT)

2021 ◽  
Author(s):  
Sheraz Raza Siddique
Keyword(s):  
Internet Of Things ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Complexity Analysis ◽  
National Security Agency ◽  
Round Function ◽  
Lightweight Block Cipher ◽  
Differential Attacks ◽  
The Internet Of Things ◽  
Feistel Structure

This project presents complexity analysis and hardware implementation of extensible modulo addition [15] encryption algorithm on a 32-bit lightweight FPGA based block cipher called INFLEX, which is designed for the internet of things (IoT) environment, supporting 64-bits key. It is designed for constrained hardware resources yet providing a highly secure scalable configuration for the variety of applications. This characteristic is obtained by the use of generalized Feistel structure combined with an improved block inflation feature. INFLEX follows a typical ARX (Add, Rotate, XOR) round function with a distinguished feature of block expansion and collapse as per user selected control string, which makes INFLEX act as a tweakable Cipher. We have shown comparison of INFLEX algorithm robustness and immunity against linear and differential attacks and demonstrated that it outperforms one of the benchmark block Ciphers Speck32/64 proposed by national security agency (NSA).

The Hardware Implementation of a Lightweight Block Cipher Algorithm and a Message Authentication Algorithm

2012 ◽  
Vol 546-547 ◽  
pp. 1489-1494
Author(s):  
Yi Kun Hu ◽  
Zun Yang Qin
Keyword(s):  
Hardware Implementation ◽  
Block Cipher ◽  
Side Channel ◽  
Message Authentication ◽  
Side Channel Attack ◽  
Side Channel Attacks ◽  
Processing Efficiency ◽  
New Family ◽  
Lightweight Block Cipher ◽  
Lightweight Cipher

Among the block cipher algorithms, AES or DES is an excellent and preferred choice for most block cipher applications. But AES and DES are not very suitable for hardware implementation because of the high cost that they require large areas of routing and the processing efficiency is low, relatively. So lightweight cipher algorithms come into beings, among which PRESENT is very competitive. Along with the structure of a message authentication algorithm ALRED, a new family of Tunable Lightweight MAC based on PRESENT is proposed, that is TuLP. However, PRESENT is not able to resist side channel attack, so is TuLP, of course. For the above reason, in this paper, we provide an improvement of PRESENT by inserting random dummy cycles as well as shuffling to strengthen the security of PRESENT against side channel attacks. We will implement PRESENT and TuLP in Verilog and do simulation on Xilinx ISim platform. At last, we would like to provide the power analyzing of Xilinx XPower.

scholarly journals Complexity analysis and hardware implementation of extensible modulo addition for lightweight block cipher in Internet of Things (IOT)

2021 ◽  
Author(s):  
Sheraz Raza Siddique
Keyword(s):  
Internet Of Things ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Complexity Analysis ◽  
National Security Agency ◽  
Round Function ◽  
Lightweight Block Cipher ◽  
Differential Attacks ◽  
The Internet Of Things ◽  
Feistel Structure

This project presents complexity analysis and hardware implementation of extensible modulo addition [15] encryption algorithm on a 32-bit lightweight FPGA based block cipher called INFLEX, which is designed for the internet of things (IoT) environment, supporting 64-bits key. It is designed for constrained hardware resources yet providing a highly secure scalable configuration for the variety of applications. This characteristic is obtained by the use of generalized Feistel structure combined with an improved block inflation feature. INFLEX follows a typical ARX (Add, Rotate, XOR) round function with a distinguished feature of block expansion and collapse as per user selected control string, which makes INFLEX act as a tweakable Cipher. We have shown comparison of INFLEX algorithm robustness and immunity against linear and differential attacks and demonstrated that it outperforms one of the benchmark block Ciphers Speck32/64 proposed by national security agency (NSA).

Protecting lightweight block cipher implementation in mobile big data computing

2016 ◽  
Vol 11 (2) ◽  
pp. 252-264
Author(s):  
Weidong Qiu ◽  
Bozhong Liu ◽  
Can Ge ◽  
Lingzhi Xu ◽  
Xiaoming Tang ◽  
...  
Keyword(s):  
Big Data ◽  
Block Cipher ◽  
Mobile Big Data ◽  
Lightweight Block Cipher ◽  
Big Data Computing

Eight-sided fortress: a lightweight block cipher

2014 ◽  
Vol 21 (1) ◽  
pp. 104-128
Author(s):  
Xuan LIU ◽  
Wen-ying ZHANG ◽  
Xiang-zhong LIU ◽  
Feng LIU
Keyword(s):  
Block Cipher ◽  
Lightweight Block Cipher

scholarly journals Orthros: A Low-Latency PRF

2021 ◽  
pp. 37-77
Author(s):  
Subhadeep Banik ◽  
Takanori Isobe ◽  
Fukang Liu ◽  
Kazuhiko Minematsu ◽  
Kosei Sakamoto
Keyword(s):  
Hardware Implementation ◽  
Block Cipher ◽  
State Of The Art ◽  
Security Analysis ◽  
Parallel Structure ◽  
Low Latency ◽  
Round Function ◽  
Minimum Latency ◽  
Primary Focus ◽  
Pseudorandom Function

We present Orthros, a 128-bit block pseudorandom function. It is designed with primary focus on latency of fully unrolled circuits. For this purpose, we adopt a parallel structure comprising two keyed permutations. The round function of each permutation is similar to Midori, a low-energy block cipher, however we thoroughly revise it to reduce latency, and introduce different rounds to significantly improve cryptographic strength in a small number of rounds. We provide a comprehensive, dedicated security analysis. For hardware implementation, Orthros achieves the lowest latency among the state-of-the-art low-latency primitives. For example, using the STM 90nm library, Orthros achieves a minimum latency of around 2.4 ns, while other constructions like PRINCE, Midori-128 and QARMA9-128- σ0 achieve 2.56 ns, 4.10 ns, 4.38 ns respectively.

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