scholarly journals Complexity analysis and hardware implementation of extensible modulo addition for lightweight block cipher in Internet of Things (IOT)

2021 ◽  
Author(s):  
Sheraz Raza Siddique
Keyword(s):  
Internet Of Things ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Complexity Analysis ◽  
National Security Agency ◽  
Round Function ◽  
Lightweight Block Cipher ◽  
Differential Attacks ◽  
The Internet Of Things ◽  
Feistel Structure

This project presents complexity analysis and hardware implementation of extensible modulo addition [15] encryption algorithm on a 32-bit lightweight FPGA based block cipher called INFLEX, which is designed for the internet of things (IoT) environment, supporting 64-bits key. It is designed for constrained hardware resources yet providing a highly secure scalable configuration for the variety of applications. This characteristic is obtained by the use of generalized Feistel structure combined with an improved block inflation feature. INFLEX follows a typical ARX (Add, Rotate, XOR) round function with a distinguished feature of block expansion and collapse as per user selected control string, which makes INFLEX act as a tweakable Cipher. We have shown comparison of INFLEX algorithm robustness and immunity against linear and differential attacks and demonstrated that it outperforms one of the benchmark block Ciphers Speck32/64 proposed by national security agency (NSA).

scholarly journals Complexity analysis and hardware implementation of extensible modulo addition for lightweight block cipher in Internet of Things (IOT)

2021 ◽  
Author(s):  
Sheraz Raza Siddique
Keyword(s):  
Internet Of Things ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Complexity Analysis ◽  
National Security Agency ◽  
Round Function ◽  
Lightweight Block Cipher ◽  
Differential Attacks ◽  
The Internet Of Things ◽  
Feistel Structure

This project presents complexity analysis and hardware implementation of extensible modulo addition [15] encryption algorithm on a 32-bit lightweight FPGA based block cipher called INFLEX, which is designed for the internet of things (IoT) environment, supporting 64-bits key. It is designed for constrained hardware resources yet providing a highly secure scalable configuration for the variety of applications. This characteristic is obtained by the use of generalized Feistel structure combined with an improved block inflation feature. INFLEX follows a typical ARX (Add, Rotate, XOR) round function with a distinguished feature of block expansion and collapse as per user selected control string, which makes INFLEX act as a tweakable Cipher. We have shown comparison of INFLEX algorithm robustness and immunity against linear and differential attacks and demonstrated that it outperforms one of the benchmark block Ciphers Speck32/64 proposed by national security agency (NSA).

scholarly journals Orthros: A Low-Latency PRF

2021 ◽  
pp. 37-77
Author(s):  
Subhadeep Banik ◽  
Takanori Isobe ◽  
Fukang Liu ◽  
Kazuhiko Minematsu ◽  
Kosei Sakamoto
Keyword(s):  
Hardware Implementation ◽  
Block Cipher ◽  
State Of The Art ◽  
Security Analysis ◽  
Parallel Structure ◽  
Low Latency ◽  
Round Function ◽  
Minimum Latency ◽  
Primary Focus ◽  
Pseudorandom Function

We present Orthros, a 128-bit block pseudorandom function. It is designed with primary focus on latency of fully unrolled circuits. For this purpose, we adopt a parallel structure comprising two keyed permutations. The round function of each permutation is similar to Midori, a low-energy block cipher, however we thoroughly revise it to reduce latency, and introduce different rounds to significantly improve cryptographic strength in a small number of rounds. We provide a comprehensive, dedicated security analysis. For hardware implementation, Orthros achieves the lowest latency among the state-of-the-art low-latency primitives. For example, using the STM 90nm library, Orthros achieves a minimum latency of around 2.4 ns, while other constructions like PRINCE, Midori-128 and QARMA9-128- σ0 achieve 2.56 ns, 4.10 ns, 4.38 ns respectively.

scholarly journals Cryptanalysis on SDDO-Based BM123-64 Designs Suitable for Various IoT Application Targets

Symmetry ◽  
2018 ◽  
Vol 10 (8) ◽  
pp. 353 ◽  
Author(s):  
Tran Phuc ◽  
Changhoon Lee
Keyword(s):  
Internet Of Things ◽  
High Speed ◽  
High Probability ◽  
Block Cipher ◽  
Algorithm Selection ◽  
Key Schedule ◽  
Boomerang Attack ◽  
Selection For ◽  
Differential Attacks

BM123-64 block cipher, which was proposed by Minh, N.H. and Bac, D.T. in 2014, was designed for high speed communication applications factors. It was constructed in hybrid controlled substitution–permutation network (CSPN) models with two types of basic controlled elements (CE) in distinctive designs. This cipher is based on switchable data-dependent operations (SDDO) and covers dependent-operations suitable for efficient primitive approaches for cipher constructions that can generate key schedule in a simple way. The BM123-64 cipher has advantages including high applicability, flexibility, and portability with different algorithm selection for various application targets with internet of things (IoT) as well as secure protection against common types of attacks, for instance, differential attacks and linear attacks. However, in this paper, we propose methods to possibly exploit the BM123-64 structure using related-key attacks. We have constructed a high probability related-key differential characteristics (DCs) on a full eight rounds of BM123-64 cipher. The related-key amplified boomerang attack is then proposed on all three different cases of operation-specific designs with effective results in complexity of data and time consumptions. This study can be considered as the first cryptographic results on BM123-64 cipher.

scholarly journals Provable Security Against a Differential Attack

1994 ◽  
Vol 23 (473) ◽  
Author(s):  
Kaisa Nyberg ◽  
Lars Ramkilde Knudsen
Keyword(s):  
Upper Bound ◽  
Provable Security ◽  
Block Cipher ◽  
Differential Cryptanalysis ◽  
Font Size ◽  
Differential Attack ◽  
Round Function ◽  
Differential Attacks

The purpose of this paper is to show that there exist DES-like iterated ciphers, which are provably resistant against differential attacks. The main result on the security of a DES-like cipher with independent round keys is Theorem 1, which gives an upper bound to the probability of <em>s</em>-round differentials, as defined in <em>Markov Ciphers and Differential Cryptanalysis </em> by X. Lai et al. and this upper bound depends only on the round function of the iterated cipher. Moreover, it is shown that there exist functions such that the probabilities of differentials are less than or equal to 2<sup><span style="font-size: x-small;">3-n</span></sup>, where <em>n</em> is the length of the plaintext block. We also show a prototype of an iterated block cipher, which is compatible with DES and has proven security against differential attacks.

Addressing Security Issues of the Internet of Things Using Physically Unclonable Functions

2021 ◽  
pp. 333-350
Author(s):  
Ishfaq Sultan ◽  
Mohammad Tariq Banday
Keyword(s):  
Internet Of Things ◽  
Hardware Implementation ◽  
Hardware Security ◽  
The Internet ◽  
Huge Number ◽  
Security Issues ◽  
Physically Unclonable Functions ◽  
Iot Devices ◽  
The Internet Of Things

The spatial ubiquity and the huge number of employed nodes monitoring the surroundings, individuals, and devices makes security a key challenge in IoT. Serious security apprehensions are evolving in terms of data authenticity, integrity, and confidentiality. Consequently, IoT requires security to be assured down to the hardware level, as the authenticity and the integrity need to be guaranteed in terms of the hardware implementation of each IoT node. Physically unclonable functions recreate the keys only while the chip is being powered on, replacing the conventional key storage which requires storing information. Compared to extrinsic key storage, they are able to generate intrinsic keys and are far less susceptible against physical attacks. Physically unclonable functions have drawn considerable attention due to their ability to economically introduce hardware-level security into individual silicon dice. This chapter introduces the notion of physically unclonable functions, their scenarios for hardware security in IoT devices, and their interaction with traditional cryptography.

The Hardware Implementation of a Lightweight Block Cipher Algorithm and a Message Authentication Algorithm

2012 ◽  
Vol 546-547 ◽  
pp. 1489-1494
Author(s):  
Yi Kun Hu ◽  
Zun Yang Qin
Keyword(s):  
Hardware Implementation ◽  
Block Cipher ◽  
Side Channel ◽  
Message Authentication ◽  
Side Channel Attack ◽  
Side Channel Attacks ◽  
Processing Efficiency ◽  
New Family ◽  
Lightweight Block Cipher ◽  
Lightweight Cipher

Among the block cipher algorithms, AES or DES is an excellent and preferred choice for most block cipher applications. But AES and DES are not very suitable for hardware implementation because of the high cost that they require large areas of routing and the processing efficiency is low, relatively. So lightweight cipher algorithms come into beings, among which PRESENT is very competitive. Along with the structure of a message authentication algorithm ALRED, a new family of Tunable Lightweight MAC based on PRESENT is proposed, that is TuLP. However, PRESENT is not able to resist side channel attack, so is TuLP, of course. For the above reason, in this paper, we provide an improvement of PRESENT by inserting random dummy cycles as well as shuffling to strengthen the security of PRESENT against side channel attacks. We will implement PRESENT and TuLP in Verilog and do simulation on Xilinx ISim platform. At last, we would like to provide the power analyzing of Xilinx XPower.

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