A DSP and FPGA Testbed for Teaching and Research of Wireless Communications

2012 ◽  
Vol 49 (3) ◽  
pp. 232-242 ◽  
Author(s):  
Julian Webber ◽  
Toshihiko Nishimura ◽  
Takeo Ohgane ◽  
Yasutaka Ogawa
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
System Development ◽  
Radio Channel ◽  
Digital Signal ◽  
Lessons Learned ◽  
Real Time System ◽  
Teaching And Research ◽  
Theoretical Concepts ◽  
Field Programmable

This paper describes the teaching and research of signal processing and communications systems that took place during the development of a real-time transceiver and radio channel testbed at Hokkaido University, Japan. Digital signal processing (DSP) concepts were taught and learnt during both the testbed system development and also the results gathering and analysis stages. The performance of a modern multiple antenna communications system is dependent on a number of key parameters, and the student interaction with such a real-time system can assist in the understanding of key but often abstract theoretical concepts. The communications algorithm and architecture overview on a signal processing board containing a Xilinx field programmable gate array (FPGA) and Analog Devices TigerSharc DSP is detailed. The lessons learned and potential uses of the testbed in both teaching and research are also described.

scholarly journals A Parallel Timing Synchronization Structure in Real-Time High Transmission Capacity Wireless Communication Systems

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 652
Author(s):  
Xin Hao ◽  
Changxing Lin ◽  
Qiuyu Wu
Keyword(s):  
Wireless Communication ◽  
Real Time ◽  
Communication Systems ◽  
Digital Signal ◽  
Transmission Capacity ◽  
Timing Synchronization ◽  
Wireless Communication Systems ◽  
Real Time System ◽  
System Clock ◽  
Field Programmable

In the past few years, parallel digital signal processing (PDSP) architectures have been intensively studied to fulfill the growing demand of channel capacity in coherent optical communication systems. However, to our knowledge, real-time timing synchronization in such architectures is until now not implemented on a Field Programmable Gate Array (FPGA). In this article, a parallel timing synchronization architecture is proposed. In the architecture, a parallel First In First Out (FIFO) structure based on an index associated rearranging method, and a dual feedback loop based on the Gardner’s algorithm, are adopted. Taking advantages of the FIFO structure, 67% Look Up Table (LUT) is saved in comparison with earlier results, meanwhile the Numerically Controlled Oscillator (NCO) is efficiently improved to meet the FPGA timing requirements for real-time performance. MATLAB simulations are run to evaluate the Bit Error Rate (BER) deterioration of the architecture. The float- and fixed-point simulation results have shown that, The BER deteriorations are less than 0.5 dB and 1 dB, respectively. Further, the implementation of the architecture on a Xilinx XC7VX485T FPGA chip is achieved. A 20 giga bit per second (Gbps) 16 Quadrature Amplitude Modulation (16QAM) real-time system is achieved at the system clock of 159.524 MHz. This work opens a new pathway to improve the transmission capacity in real-time wireless communication systems.

Real-time signal processing in field programmable gate array based digital gamma-ray spectrometer

2020 ◽  
Vol 91 (10) ◽  
pp. 104707
Author(s):  
Yinyu Liu ◽  
Hao Xiong ◽  
Chunhui Dong ◽  
Chaoyang Zhao ◽  
Quanfeng Zhou ◽  
...  
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Gamma Ray ◽  
Time Signal ◽  
Gamma Ray Spectrometer ◽  
Field Programmable ◽  
Gate Array ◽  
Real Time Signal Processing

An Accelerator for Real-Time Digital Signal Processing with Microprocessors

1987 ◽  
Vol 24 (1) ◽  
pp. 65-72
Author(s):  
C. Ward
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Real Time ◽  
Digital Signal ◽  
Fir Filters ◽  
Minimal Cost ◽  
Hands On

An accelerator consisting of a fast digital multiplier and A/D and D/A converters is designed for the BBC microcomputer. The circuit enables ‘hands-on’ experience of digital signal processing to be provided at minimal cost. Examples of implementations of FIR filters and an autocorrelation algorithm are provided.

scholarly journals Real-time digital signal processing for live electro-optic imaging

2009 ◽  
Vol 17 (18) ◽  
pp. 15641 ◽  
Author(s):  
Kiyotaka Sasagawa ◽  
Atsushi Kanno ◽  
Masahiro Tsuchiya
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Real Time ◽  
Digital Signal ◽  
Electro Optic

The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

2012 ◽  
Vol 571 ◽  
pp. 534-537
Author(s):  
Bao Feng Zhang ◽  
De Hu Man ◽  
Jun Chao Zhu
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Distributed Algorithm ◽  
Design Method ◽  
Fir Filter ◽  
Experimental Results ◽  
Linear Phase ◽  
Design And Implementation ◽  
Field Programmable

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

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