scholarly journals Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes

2013 ◽  
Author(s):  
Vicente Lorente ◽  
Alejandro Valero ◽  
Julio Sahuquillo ◽  
Salvador Petit ◽  
Ramon Canal ◽  
...  
Keyword(s):  
Low Power ◽  
Error Recovery ◽  
L1 Data ◽  
Data Caches

scholarly journals Compiler-managed partitioned data caches for low power

2007 ◽  
Vol 42 (7) ◽  
pp. 237-247 ◽  
Author(s):  
Rajiv Ravindran ◽  
Michael Chu ◽  
Scott Mahlke
Keyword(s):  
Low Power ◽  
Data Caches ◽  
Partitioned Data

Novel SRAM bias control circuits for a low power L1 data cache

NORCHIP 2012 ◽  
2012 ◽  
Author(s):  
A. Seyedi ◽  
A. Armejach ◽  
A. Cristal ◽  
O. S. Unsal ◽  
M. Valero
Keyword(s):  
Low Power ◽  
Data Cache ◽  
L1 Data ◽  
Control Circuits

Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor

2020 ◽  
Author(s):  
Antonio G. M. Strollo ◽  
Davide De Caro ◽  
Ettore Napoli ◽  
Nicola Petra ◽  
Gennaro Di Meo
Keyword(s):  
Low Power ◽  
Error Recovery

Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery

2019 ◽  
Vol 66 (1) ◽  
pp. 189-202 ◽  
Author(s):  
Honglan Jiang ◽  
Cong Liu ◽  
Fabrizio Lombardi ◽  
Jie Han
Keyword(s):  
Low Power ◽  
Error Recovery

scholarly journals An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

2017 ◽  
Vol 16 (5s) ◽  
pp. 1-19 ◽  
Author(s):  
Soumya Basu ◽  
Loris Duch ◽  
RubÉn Braojos ◽  
Giovanni Ansaloni ◽  
Laura Pozzi ◽  
...  
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
Error Recovery ◽  
Ultra Low Power ◽  
Processing Architecture
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