Fault Analysis and Simulation of Large Scale Industrial Mixed-Signal Circuits

2013 ◽  
Author(s):  
Ender Yilmaz ◽  
Geoff Shofner ◽  
LeRoy Winemberg ◽  
Sule Ozev
Keyword(s):  
Large Scale ◽  
Fault Analysis ◽  
Mixed Signal ◽  
Mixed Signal Circuits

A Novel Method Towards Time-Efficient Fault Analysis of Analog and Mixed-Signal Circuits

2017 ◽  
Vol 26 (08) ◽  
pp. 1740005
Author(s):  
Juraj Brenkuš ◽  
Viera Stopjaková ◽  
Viera Čerňanová ◽  
Daniel Arbet ◽  
Lukáš Nagy ◽  
...  
Keyword(s):  
Fault Simulation ◽  
Complex Impedance ◽  
Fault Analysis ◽  
Mixed Signal ◽  
Simulation Methodology ◽  
Experimental Application ◽  
Mixed Signal Circuits ◽  
Efficient Calculation ◽  
Novel Method ◽  
Impedance Calculation

A novel method of nodal impedance calculation is presented in this paper. This method is capable of time-efficient calculation of arbitrary two-point complex impedance in an analog and mixed-signal circuit and could improve the development time of impedance-based tests both in DC and AC domain. A fault simulation methodology based on the proposed method is described in detail. Several experiments are provided that prove the time efficiency of the method. Experimental application showing the benefits of the method on a real circuit is provided as well.

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

2009 ◽  
Vol 17 (10) ◽  
pp. 1405-1418 ◽  
Author(s):  
E. Salman ◽  
R. Jakushokas ◽  
E.G. Friedman ◽  
R.M. Secareanu ◽  
O.L. Hartin
Keyword(s):  
Large Scale ◽  
Noise Analysis ◽  
Substrate Noise ◽  
Mixed Signal ◽  
Mixed Signal Circuits

The Design and Validation of DFT System for Mixed-Signal Circuits Based on JTAG

2013 ◽  
Vol 427-429 ◽  
pp. 636-639
Author(s):  
Guo Gang Liao ◽  
Jun Li
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Test System ◽  
Design For Test ◽  
Boundary Scan ◽  
Electronic Control ◽  
Integrity Test ◽  
Mixed Signal ◽  
Mixed Signal Circuits ◽  
Electronic Control System

Nowadays with the increases of the density of large scale integrated circuits, researches of Design for Test (DFT) become more and more important, JTAG (JTAG: Joint Test Action Group, also called Boundary Scan ) has been widely used in test area , which improves the testability and reliability of mixed-signal circuits. This paper puts forward a scheme to design a Built-in Test System (BITS) based on boundary scan technology. The BITS is realized in a weapon electronic control system, which is composed of mixed-signal circuits including ARM, AD/DA, FPGA, etc. With this method, several test experiments are carried out in the BITS, which include infrastructure integrity test, interconnect test, cluster test, AD/DA test and so on. The results of experiments show that the Built-in Test System based on JTAG can work normally, which is able to reduce effectively the complexity and the time of test. In a word, the capability of BITS is viable and the system is a virtual tool in the process of DFT design and application.

scholarly journals Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency

2018 ◽  
Vol 8 (4) ◽  
pp. 34 ◽  
Author(s):  
Vishal Saxena ◽  
Xinyu Wu ◽  
Ira Srivastava ◽  
Kehan Zhu
Keyword(s):  
Machine Learning ◽  
Energy Efficiency ◽  
Deep Learning ◽  
Large Scale ◽  
Learning Algorithms ◽  
Memory Devices ◽  
Cognitive Computing ◽  
Mixed Signal ◽  
Von Neumann ◽  
Emerging Memory

The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency.

Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods

2008 ◽  
Vol 27 (12) ◽  
pp. 2223-2235 ◽  
Author(s):  
David Walter ◽  
Scott Little ◽  
Chris Myers ◽  
Nicholas Seegmiller ◽  
Tomohiro Yoneda
Keyword(s):  
Mixed Signal ◽  
Mixed Signal Circuits ◽  
Symbolic Methods
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