An Area-Power Efficient Denoising Hardware Architecture for Real EOG Signal

This paper presents an optimized noise reduction hardware architecture for real electrooculogram (EOG) system. The proposed denoise architecture is developed using differential evolution (DE) algorithm. The algorithm design the filter with fewer sign-power-of-two (SPT) terms to optimize the denoise filter hardware with desired frequency response. The proposed denoise filter architecture with a DE coefficient set uses shift and add approach and is implemented in gate-level Verilog HDL. The real EOG denoise filter’s functionality is checked with Altera DSP Builder and synthesized using Cadence RTL compiler. Both FPGA and ASIC synthesis results are compared with the recently published works. The area and power consumption results show that the proposed filter occupies less area and with low power consumption as compared to the existing architectures.

VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes

This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.