Adaptive Noise-Resistant Low-Power ASK Demodulator Design in UHF RFID Chips

This paper presents a new signal demodulator for ultra-high frequency (UHF) radio frequency identification (RFID) tag chips. The demodulator is used to demodulate amplitude shift keying (ASK) modulated signals with the advantages of high noise immunity, large input range and low power consumption. The demodulator consists of a charge pump, an envelope detector, and a comparator. In particular, the demodulator provides a hysteresis input signal to the comparator through two envelope detectors, resulting in better noise immunity. The demodulator is based on a standard 0.13 µm CMOS process. The demodulator is suitable for demodulating high frequency signals at 900 MHz with a data rate of 128 Kbps and can operate up to 78 °C. The input signal has a peak of 1.2 V and consumes as little as 113.6 nW. The demodulator also has a noise immunity threshold of approximately 3.729 V.

The Design Methodology of Fully Digital Pulse Width Modulation

This paper describes the design methodology and calibration technique for a low-power digital pulse width modulation demodulator to enhance its robustness against the process, voltage, and temperature variations in different process corners, in addition to intra-die variability, which makes it a very good choice for implantable monitoring sensors. Furthermore, the core of the proposed demodulator is fully digital. Thus, along with the proposed design methodology, the proposed demodulator can be simply redesigned in advanced subnanometer CMOS technologies without much difficulty as compared to analog demodulators. The proposed demodulator consists of an envelope detector, a digitizer, a ring oscillator, and a data detector with digital calibration. All the proposed circuits are designed and simulated in the standard 1P9M TSMC’s 40 nm CMOS technology. Simulation results have shown that the circuit is capable of demodulating and recovering data from an input signal with a carrier frequency of 13.56 MHz and a data rate of 143 kB/s with an average power consumption of 5.62 μW.

A High Efficiency Low Noise RF-to-DC Converter Employing Gm-Boosting Envelope Detector and Offset Canceled Latch Comparator

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.

Low-Power Sensor Interface with a Switched Inductor Frequency Selective Envelope Detector

With the growing need to understand our surroundings and improved means of sensor manufacturing, the concept of Internet of Things (IoT) is becoming more interesting. To enable continuous monitoring and event detection by IoT, the development of low power sensors and interfaces is required. In this work we present a novel, switched inductor based acoustic sensor interface featuring a bandpass filter and envelope detector, perform a sensitivity, frequency selectivity, and power consumption analysis of the circuit, and present its design parameters and their qualitative influence on circuit characteristics. We develop a prototype and present experimental characterization of the interface and its operation with input signals up to 20 mV peak-to-peak, at low acoustic frequencies from 100 Hz to 1 kHz. The prototype achieves a sensitivity of approximately 2 mV/mV in the passband, a four times lower sensitivity in the stopband, and a power consumption of approximately 3.31 µW. We compare the prototype interface to an interface consisting of an active bandpass filter and a passive voltage doubler using a prerecorded speedboat signal.

A High Conversion Gain Envelope Detector with Wide Input Range for Simultaneous Wireless Information and Power Transfer System

Wireless sensors networks (WSN) have been gradually facilitating the pervasive connectivity of wireless sensor nodes. A greater number of wireless sensors have been used in different aspects of our life. However, limited device battery life restricts the applications of large-scale WSN. This paper presents a batteryless envelope detector with radio frequency energy harvesting (RFEH) for wireless sensor nodes, which enables simultaneous wireless information and power transfer (SWIPT). The envelope detector is designed for small modulation index AM signals with large amplitude variations. Therefore, the envelope detector is supposed to have wide input range while achieving a high conversion gain. We proposed an adaptive biasing technique in order to extend the input range of envelope detector. The input differential pair is adaptively biased through a feedback loop to overcome the variation of bias point when the amplitude of input signal changes. The cross coupled rectifier and DC-DC boost converter with maximum power point tracking (MPPT) are presented against power conversion efficiency (PCE) degradation of RF rectifier with the input power varying. The adaptive biased envelope detector is theoretically analyzed by square law MOSFET model. Designed with 0.18 μm complementary-metal-oxide-semiconductor (CMOS) standard process, the power consumption of proposed envelope detector is 9 μW. Simulated with a 915 MHz AM input signal with 2 Mbps data rate and 0.05 modulation index, the proposed envelope detector achieves 20.37 dB maximum conversion gain when the amplitude of input signal is 0.5 V, and the PCE of energy harvesting circuits achieves 55.2% when input power is –12.5 dBm.