An Area-Power Efficient Denoising Hardware Architecture for Real EOG Signal
This paper presents an optimized noise reduction hardware architecture for real electrooculogram (EOG) system. The proposed denoise architecture is developed using differential evolution (DE) algorithm. The algorithm design the filter with fewer sign-power-of-two (SPT) terms to optimize the denoise filter hardware with desired frequency response. The proposed denoise filter architecture with a DE coefficient set uses shift and add approach and is implemented in gate-level Verilog HDL. The real EOG denoise filter’s functionality is checked with Altera DSP Builder and synthesized using Cadence RTL compiler. Both FPGA and ASIC synthesis results are compared with the recently published works. The area and power consumption results show that the proposed filter occupies less area and with low power consumption as compared to the existing architectures.