Performing Multithreading and Multitasking on Linux Operating System

In a modern computing system, there are usually several concurrent application processes which compete for CPU. The Operating System (OS), amongest other duties, is responsible for the effective and efficient allocation of those resources. The OS module which handles resource allocation is called scheduler. On the basis of the type of OS to be realized, different scheduling policies may be implemented. All modern computers have the capability of Multitasking and Multithreading. This project focuses on developing an single process like Matrix Multiplication of size 1000 * 1000 having multiple code segments threads that run concurrently on 2.33 GHz quad-core i3 Processor and 900 MHz quad-core ARM Cortex-A7 and to make comparison between them. This project also develops an method for running multiple tasks at a time on particular isolated cpu core on 2.33 GHz quad-core i3 Processor and 900 MHz quad-core ARM Cortex-A7 and to make comparison between them.

Multiple-Code Technique for Multi-Rate Transmissions in Optical Packet Switching Networks Based on OCDMA Labels

Supporting multi-rate transmission is an essential factor in current optical packet switching (OPS) networks. In this paper, the author studied a multi-rate scheme capable of forwarding packets with different signal rates based on label switching. The multiple-code (MC) technique was employed to label a packet by conveying its payload bits to multiple optical code-division multiple-access (OCDMA) labels. Spectral-amplitude-coding (SAC), which represents the chips in an OCDMA code as a set of wavelengths, was introduced to remove the multiple-access interference (MAI) from the overlapping among labels. The author tested the system effectiveness by conducting numerical analysis to formulate bit-error probability (BEP) and spectral efficiency (SE). The simulation results showed that the proposed network had a stable BEP performance when switching the packet flows of multiple data-rates.

A scalable ASIP for BP Polar decoding with multiple code lengths

In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with state-of-art Polar decoders reveals PASIP’s high area efficiency.