Node-Subset Scheduling with a Subset-Reset Mechanism for the Decoding Algorithm of Nonbinary LDPC Codes

For the conventional extended min-sum (EMS) algorithm, all check nodes update their check-to-variable (C2V) messages in every iteration. Selected scheduling, which reduces the number of check nodes for message updating in one iteration, can effectively reduce the complexity of the decoding algorithm, but it also lead to some performance degradation. With the introduction of a metric based on node stability, we propose stability-based node-subset scheduling (SNS) for the EMS algorithm, which can improve the performance of node-subset scheduling (NS). Second, to further improve the decoding performance of SNS while maintaining low complexity, we propose the SNS-EMS algorithm with a subset-reset mechanism (RSNS-EMS) based on the abnormal stability found in the processing node subset, which will cause the estimated codeword to fail to converge. The RSNS-EMS algorithm enhances performance through a sliding window detection and reset mechanism, and it resets the elements in the processing node subset to force all check nodes to update new messages when abnormal stability is detected. The simulation results show that the proposed algorithm can reduce complexity by approximately 25% with negligible performance degradation.

Efficient Pipelined Broadcast with Monitoring Processing Node Status on a Multi-Core Processor

This paper presents an efficient pipelined broadcasting algorithm with the inter-node transmission order change technique considering the communication status of processing nodes. The proposed method changes the transmission order for the broadcast operation based on the communication status of processing nodes. When a broadcast operation is received, a local bus checks the remaining pre-existing transmission data size of each processing node; it then transmits data according to the changed transmission order using the status information. Therefore, the synchronization time can be hidden for the remaining time, until the pre-existing data transmissions finish; as a result, the overall broadcast completion time is reduced. The simulation results indicated that the speed-up ratio of the proposed algorithm was up to 1.423, compared to that of the previous algorithm. To demonstrate physical implementation feasibility, the message passing engine (MPE) with the proposed broadcast algorithm was designed by using Verilog-HDL, which supports four processing nodes. The logic synthesis results with TSMC 0.18 μm process cell libraries show that the logic area of the proposed MPE is 2288.1 equivalent NAND gates, which is approximately 2.1% of the entire chip area. Therefore, performance improvement in multi-core processors is expected with a small hardware area overhead.

A Fast Firefly Algorithm

In this study, the advantages of the parallel compution paradigms are utilized in a recent optimization algorithm, firefly algorithm. In the proposed implementation, the population is divided into subpopulations and each subpopulation is run on a different processing node. From the results on commonly used benchmark functions, the proposed model enhances the computation cost without comprosing on the solution quality.