Modeling cache performance for embedded systems

This paper presents a cache performance model for embedded systems. The need for efficient cache design in embedded systems has led to the exploration of various methods of design for optimal cache configurations for embedded processor. Better users’ experiences are realized by improving performance parameters of embedded systems. This work presents a cache hit rate estimation model for embedded systems that can be used to explore optimal cache configurations using Bourneli’s binomial cumulative probability based on application of reuse distance profiles. The model presented was evaluated using three mibench benchmarks which are bitcount, basicmath and FFT for 4kb, 8kb, 16kb, 32kb and 64kb sizes of cache under 2-way, 4-ways, 8-ways and 16-ways set associative configurations, all using least recently-used (LRU) replacement policy. The results were compared with the results obtained using sim-cheetah from simplescalar simulators suite. The mean errors for bitcount, basicmath, and FFT benchmarks are 0.0263%, 2.4476%, and 1.9000% respectively. Therefore, the mean error for the three benchmarks is equal to 1.4579%. The margin of errors in the results was below 5% and within the acceptable limits showing that the model can be used to estimate hit rates of cache and to explore cache design options.

HIERARCHICAL SET-ASSOCIATE CACHE FOR HIGH-PERFORMANCE AND LOW-ENERGY ARCHITECTURE

This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are k times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different cache configurations. The results reveal that the proposed scheme exhibits a higher hit ratio compared to the two well-known mapping schemes, namely set-associative and direct mapping. Moreover, the area and power consumption of this scheme is less than full-associative scheme.