HIERARCHICAL SET-ASSOCIATE CACHE FOR HIGH-PERFORMANCE AND LOW-ENERGY ARCHITECTURE

2006 ◽  
Vol 15 (06) ◽  
pp. 861-880 ◽  
Author(s):  
HAMID R. ZARANDI ◽  
SEYED GHASSEM MIREMADI
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Low Energy ◽  
Hierarchical Level ◽  
Hierarchy Level ◽  
Direct Mapping ◽  
Division Factor ◽  
Cache Scheme ◽  
Cache Configurations

This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are k times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different cache configurations. The results reveal that the proposed scheme exhibits a higher hit ratio compared to the two well-known mapping schemes, namely set-associative and direct mapping. Moreover, the area and power consumption of this scheme is less than full-associative scheme.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

High-Performance and Low-Energy Loss Organic Solar Cells with Non-fused Ring Acceptor by Alkyl Chain Engineering

2021 ◽  
pp. 129768
Author(s):  
Dou Luo ◽  
Xue Lai ◽  
Nan Zheng ◽  
Chenghao Duan ◽  
Zhaojin Wang ◽  
...  
Keyword(s):  
Solar Cells ◽  
Energy Loss ◽  
Organic Solar Cells ◽  
High Performance ◽  
Alkyl Chain ◽  
Low Energy ◽  
Fused Ring

Realizing Stable High‐Performance and Low‐Energy‐Loss Ternary Photovoltaics through Judicious Selection of the Third Component

Solar RRL ◽  
2021 ◽  
pp. 2100450
Author(s):  
Bing-Huang Jiang ◽  
Yi-Peng Wang ◽  
Yu-Wei Su ◽  
Jia-Fu Chang ◽  
Chu-Chen Chueh ◽  
...  
Keyword(s):  
Energy Loss ◽  
High Performance ◽  
Low Energy ◽  
The Third ◽  
Selection Of

scholarly journals Simultaneous Monitoring of Particle-Bound PAHs Inside a Low-Energy School Building and Outdoors over Two Weeks in France

Atmosphere ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 108
Author(s):  
Céline Liaud ◽  
Sarah Chouvenc ◽  
Stéphane Le Calvé
Keyword(s):  
Particle Size ◽  
Air Quality ◽  
High Performance ◽  
Sampling Period ◽  
Temporal Variations ◽  
Ventilation Rate ◽  
Low Energy ◽  
Total Particle ◽  
Polycyclic Aromatic ◽  
Individual Pahs

The emergence of new super-insulated buildings to reduce energy consumption can lead to a degradation of the indoor air quality. While some studies were carried out to assess the air quality in these super-insulated buildings, they were usually focused on the measurement of gas phase pollutants such as carbon dioxide and volatile organic compounds. This work reports the first measurements of Polycyclic Aromatic Hydrocarbons (PAHs) associated with particles as a function of time and particle size in a low-energy building. The airborne particles were collected indoors and outdoors over three to four days of sampling using two three-stage cascade impactors allowing to sample simultaneously particles with aerodynamic diameter Dae > 10 µm, 2.5 µm < Dae < 10 µm, 1 µm < Dae < 2.5 µm, and Dae < 1 µm. The 16 US-EPA priority PAHs were then extracted and quantified by high-performance liquid chromatography (HPLC) coupled to fluorescence detection. The resulting total particle concentrations were low, in the ranges 3.73 to 9.66 and 0.60 to 8.83 µg m-3 for indoors and outdoors, respectively. Thirteen PAHs were always detected in all the samples. The total PAH concentrations varied between 290 and 415 pg m−3 depending on the particle size, the environment (indoors or outdoors) and the sampling period considered. More interestingly, the temporal variations of individual PAHs highlighted that high molecular weight PAHs were mainly associated to the finest particles and some of them exhibited similar temporal behaviors, suggesting a common emission source. The indoor-to-outdoor concentration ratios of individual PAH were usually found close to or less than 1, except during the event combining rainy conditions and limited indoor ventilation rate.

Constructing a Bioinformatics Platform with Web and Mobile Services Based on NVIDIA Jetson TK1

2015 ◽  
Vol 7 (4) ◽  
pp. 57-73 ◽  
Author(s):  
Chun-Yuan Lin ◽  
Jin Ye ◽  
Che-Lun Hung ◽  
Chung-Hung Wang ◽  
Min Su ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Performance Computing ◽  
Graphics Processing Units ◽  
High Performance ◽  
Low Cost ◽  
Research Direction ◽  
Mobile Services ◽  
Performance Ratio ◽  
The Cost ◽  
Performance Computing

Current high-end graphics processing units (abbreviate to GPUs), such as NVIDIA Tesla, Fermi, Kepler series cards which contain up to thousand cores per-chip, are widely used in the high performance computing fields. These GPU cards (called desktop GPUs) should be installed in personal computers/servers with desktop CPUs; moreover, the cost and power consumption of constructing a high performance computing platform with these desktop CPUs and GPUs are high. NVIDIA releases Tegra K1, called Jetson TK1, which contains 4 ARM Cortex-A15 CPUs and 192 CUDA cores (Kepler GPU) and is an embedded board with low cost, low power consumption and high applicability advantages for embedded applications. NVIDIA Jetson TK1 becomes a new research direction. Hence, in this paper, a bioinformatics platform was constructed based on NVIDIA Jetson TK1. ClustalWtk and MCCtk tools for sequence alignment and compound comparison were designed on this platform, respectively. Moreover, the web and mobile services for these two tools with user friendly interfaces also were provided. The experimental results showed that the cost-performance ratio by NVIDIA Jetson TK1 is higher than that by Intel XEON E5-2650 CPU and NVIDIA Tesla K20m GPU card.

scholarly journals Reducing Energy Consumption Strategies in University Buildings in Egypt

2018 ◽  
Vol 2 (3) ◽  
pp. 112
Author(s):  
Amal Ahmed Abdou ◽  
Iman Osama Abd El Gwad ◽  
Ayman Alsayed Altaher Mahmoud
Keyword(s):  
Energy Consumption ◽  
High Performance ◽  
Low Cost ◽  
Integrated Design ◽  
Design Strategy ◽  
Low Energy ◽  
Main Concern ◽  
University Buildings ◽  
Low Performance ◽  
Consumption Strategies

Egyptian universities had the most powerful buildings that encourage sustainable development. Sustaining university buildings had been the main concern, thus the development focused on different aspects (social, sociological, bio-life, physical, healthy surroundings, etc.). In recent times, the main problem facing university buildings has been the high consumption of energy despite the low performance. This problem affected the interior areas and spaces used by the majority of students. The issue hindered the learning environment—which should be designed to facilitate high academic performance—from achieving its purpose. Fixing the problem required finding the errors applied in the planning policy, in order to integrate low energy consumption with high performance. This paper analyzes the design strategy, low energy design strategy, and its analysis systems in order to integrate them with the analysis of four case studies in comparative methodology. This approach helps in achieving effective observation to implement principles, policy, criteria, and strategies. The method of the paper shall help with coming up with an efficient vision to create the integrated design strategy for constructing university buildings in Egypt. The solution is characterized by low-cost energy consumption that is applicable to the conditions in Egypt and is in synchronization with sustainability as a whole vision.

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