Investigating the Impact of Self-Heating Effects on Some Thermal and Electrical Characteristics of Dielectric Pocket Gate-All-Around (DPGAA) MOSFETs

The dielectric pocket gate-all-around (DPGAA) MOSFET is being considered the best suited candidate for ULSI electronic chips because of excellent electrostatic control over the channel. However, the phenomena of self-heating and hot carrier injection (HCI) severely affect the performance of the device, and make the behaviour of the DPGAA FET very unpredictable. In the present article, a comprehensive investigation under the influence of self-heating effects has been done for the variation in the lattice and carrier temperature against spacer length, ambient temperature, device length, and thermal contact resistance including ON and Off currents with gate bias voltage (VGS). In order to analyse the SHEs, the hydrodynamic (HD) and thermodynamic (TD) transport models have been used for three-dimensional (3D) electrothermal (ET) simulation. The Lucky (hot carrier injection) model has been used to study the HCI degradation in DPGAA MOSFET using Sentaurus 3D TCAD simulator.

3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.

3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.