An Optimized Approach to Generate Multicarrier Radar Signal Using Computationally Efficient Algorithm

MCPC radar signal accedes the property of orthogonal frequency division multiplexing. A term in the complex envelope expression for MCPC shows similarity to the twiddle factor which paved a way for generating MCPC signal by incorporating computationally efficient algorithm which produces envelope as similar with conventional method along with the reduction in the number of computations. Various transforms were validated, among all of them FFT implementation results gave rise to the least PMEPR which is the most essential for using power amplifiers in the faithful manner.

Multi path pipelined architecture with twin parallel processing after second stage for high-speed FFT

This paper presents review on different pipelined FFT architectures and proposes a new pipelined FFT architecture with twin parallel processing after second stage. The proposed architecture follows a novel data flow path, Twiddle factor generation and multiplication is implemented by multiplier and shift registers. The first two stages are implemented by multipath pipelined form after that it follows twin parallel form. The twin parallel form consists of two pipelined units simultaneously generates FFT output values. This architecture reduces latency in a greater extent with a smaller cost of hardware. The proposed architecture compared with previous architectures. The proposed architecture is implemented for Radix-2 and Radix-22 DIF FFT. The throughput of proposed architecture is four.

An efficient floating-point FFT twiddle factor implementation based on adaptive angle recoding CORDIC algorithm

In this paper, a single-precision floating-point FFT twiddle factor (TF) implementation is proposed. The architecture is based on the Adaptive Angle Recoding CORDIC (AARC) algorithm. The TF design was built and verified on Altera Stratix IV FPGA chip and 65nm SOTB synthesis. The FPGA implementation had 103.9 MHz maximum frequency, throughput result of 16.966 Mega-Sample per second (MSps), and resources utilization of 7.747 ALUTs and 625 registers. On the other hand, the SOTB synthesis has 16.858 standard cells on an area of 298x291 μm2, 166 MHz maximum frequency, and the speed of 27.107 MSps. The accuracy results were 1.133E-10 Mean-Square-Error (MSE) and about 26 part-per-million (ppm) maximum error.