A Generalized Frame-Level FSBM FLSA Architecture

2013 ◽  
Vol 284-287 ◽  
pp. 2915-2920
Author(s):  
Li Chang Liu ◽  
Jong Chih Chien ◽  
Yu Wei Hsu
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
Block Size ◽  
Block Matching ◽  
Full Detail ◽  
Pipelined Architectures ◽  
Block Level ◽  
Generalized Frame ◽  
Block Based ◽  
Memory Accesses

Block-based motion estimation plays important roles in video applications such as video compression to detect movements as well as remove temporal redundancies between successive frames. Full-search block-matching (FSBM) is the preferred algorithm for accurate motion estimation. Frame-level pipelined systolic array (FLSA) FSBM architectures have advantages over block-level pipelined architectures in their simpler control and reduced number of memory accesses. In this paper, a frame-level pipelined FSBM motion estimation architecture using array processor for any square, N×N, block size is presented in full detail.

Adaptive Return Prediction Block Matching Algorithms for Video Coding

2011 ◽  
Vol 145 ◽  
pp. 277-281
Author(s):  
Vaci Istanda ◽  
Tsong Yi Chen ◽  
Wan Chun Lee ◽  
Yuan Chen Liu ◽  
Wen Yen Chen
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
Web Site ◽  
Motion Vector ◽  
Temporal Correlation ◽  
Block Matching ◽  
Asynchronous Learning ◽  
Learning And Teaching ◽  
Block Motion ◽  
Reconstruction Image

As the development of network learning, video compression is important for both data transmission and storage, especially in a digit channel. In this paper, we present the return prediction search (RPS) algorithm for block motion estimation. The proposed algorithm exploits the temporal correlation and characteristic of returning origin to obtain one or two predictive motion vector and selects one motion vector, which presents better result, to be the initial search center. In addition, we utilize the center-biased block matching algorithms to refine the final motion vector. Moreover, we used adaptive threshold technique to reduce the computational complexity in motion estimation. Experimental results show that RPS algorithm combined with 4SS, BBGDS, and UCBDS effectively improves the performance in terms of mean-square error measure with less average searching points. On the other hand, accelerated RPS (ARPS) algorithm takes only 38% of the searching computations than 3SS algorithm, and the reconstruction image quality of the ARPS algorithm is superior to 3SS algorithm about 0.30dB in average overall test sequences. In addition, we create an asynchronous learning environment which provides students and instructors flexibility in learning and teaching activities. The purpose of this web site is to teach and display our researchable results. Therefore, we believe this web site is one of the keys to help the modern student achieve mastery of complex Motion Estimation.

Design and Memory Optimization of Motion Estimation Module for H.264/AVC Encoder

2011 ◽  
Vol 179-180 ◽  
pp. 1350-1355
Author(s):  
Duo Li Zhang ◽  
Chuan Jie Wang ◽  
Yu Kun Song ◽  
Gao Ming Du ◽  
Xian Wen Cheng
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
Estimation Accuracy ◽  
Memory Optimization ◽  
Search Window ◽  
Pipeline Architecture ◽  
Macro Block ◽  
Block Level ◽  
Organization Strategy ◽  
On Chip

H.264/AVC standard has been widely used in video compression at various kinds of application domain. Motion estimation takes the most calculation workload of H.264/AVC encoder. Memory optimization has played an even more important role in encoder design. Firstly, dependency relation between motion vectors was analyzed and removed at a little cost of estimation accuracy decrement, and then a 3-stage macro-block level pipeline architecture was proposed to increase parallel process ability of motion estimation. Then an optimized memory organization strategy of reference frame data was put forward, aiming at avoiding row changing frequently in SDRAM access. Finally, based on the 3-stage pipeline structure, a shared cyclic search window memory was proposed: 1) data relativity between adjacent macro-block was analyzed, 2) and search window memory size was elaborated, 3) and then a slice based structure and the work process were discussed. Analysis and experiment result show that 50% of on chip memory resource and cycles for off chip SDRAM access can be saved. The whole design was implemented with Verilog HDL and integrated into a H.264 encoder, which can demo 1280*720@30 video successfully at frequency of 120MHz under a cyclone III FPGA development board.

High Performance Architecture of Motion Estimation Algorithm for Video Compression

2016 ◽  
Vol 25 (08) ◽  
pp. 1650083
Author(s):  
P. Muralidhar ◽  
C. B. Rama Rao
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
Estimation Algorithm ◽  
Block Matching ◽  
High Definition ◽  
Systolic Architecture ◽  
Hardware Architectures ◽  
Computationally Intensive ◽  
Full Search

Motion estimation (ME) is a highly computationally intensive operation in video compression. Efficient ME architectures are proposed in the literature. This paper presents an efficient low computational complexity systolic architecture for full search block matching ME (FSBME) algorithm. The proposed architecture is based on one-bit transform-based full search (FS) algorithm. The proposed ME hardware architectures perform FS ME for four macroblocks (MBs) in parallel. The proposed hardware architecture is implemented in VHDL. The FSBME hardware consumes 34% of the slices in a Xilinx Vertex XC6vlx240T FPGA device with a maximum frequency of 133[Formula: see text]MHz and is capable of processing full high definition (HD) ([Formula: see text]) frames at a rate of 60 frames per second.

scholarly journals High Speed Parallel SAD Architecture Implementation on FPGA for HEVC encoder

2019 ◽  
Vol 8 (6) ◽  
pp. 1235-1238
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Speed ◽  
High Performance ◽  
High Efficiency ◽  
Block Size ◽  
Video Encoding ◽  
Computational Time ◽  
Absolute Difference ◽  
Asymmetric Mode

Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant reduction in delay and increase in frequency in comparison with results of other parallel architectures.

scholarly journals A Complexity and Quality Evaluation of Block Based Motion Estimation Algorithms

10.14311/668 ◽  
2005 ◽  
Vol 45 (1) ◽  
Author(s):  
S. Usama ◽  
M. Montaser ◽  
O. Ahmed
Keyword(s):  
Performance Evaluation ◽  
Motion Estimation ◽  
Video Compression ◽  
Quality Evaluation ◽  
Point Of View ◽  
Video Sequences ◽  
Compression Algorithms ◽  
Estimation Algorithms ◽  
Block Based ◽  
A Performance

Motion estimation is a method, by which temporal redundancies are reduced, which is an important aspect of video compression algorithms. In this paper we present a comparison among some of the well-known block based motion estimation algorithms. A performance evaluation of these algorithms is proposed to decide the best algorithm from the point of view of complexity and quality for noise-free video sequences and also for noisy video sequences. 

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