Reference Oversampling PLL Achieving -256-dB FoM and -78-dBc Reference Spur

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2021.3089930 ◽

2021 ◽

pp. 1-1

Author(s):

Ji-Hwan Seol ◽

Kyojin Choo ◽

David Blaauw ◽

Dennis Sylvester ◽

Taekwang Jang

Keyword(s):

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A Reference Oversampling Digital Phase-Locked Loop with -240 dB FOM and -80 dBc Reference Spur

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778010 ◽

2019 ◽

Author(s):

Ji-Hwan Seol ◽

Dennis Sylvester ◽

David Blaauw ◽

Taekwang Jang

Keyword(s):

Phase Locked Loop ◽

Digital Phase ◽

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AMASS PLL: An Active-Mixer-Adopted Sub-Sampling PLL Achieving an FOM of −255.5DB and a Reference Spur of −66.6DBC

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502425 ◽

2018 ◽

Author(s):

Dhon-Gue Lee ◽

Patrick P. Mercier

Keyword(s):

Active Mixer ◽

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A 0.8∼1.3 GHz multi-phase injection-locked PLL using capacitive coupled multi-ring oscillator with reference spur suppression

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993634 ◽

2017 ◽

Author(s):

Ruixin Wang ◽

Fa Foster Dai

Keyword(s):

Ring Oscillator ◽

Reference Spur ◽

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28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and <-100dBc reference spur for 802.11ac

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) ◽

10.1109/isscc.2014.6757518 ◽

2014 ◽

Author(s):

Yu-Li Hsueh ◽

Lan-Chou Cho ◽

Chih-Hsien Shen ◽

Yi-Chien Tsai ◽

Tzu-Chan Chueh ◽

...

Keyword(s):

Frequency Synthesizer ◽

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A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2021.3094934 ◽

2021 ◽

pp. 1-1

Author(s):

Yunbo Huang ◽

Yong Chen ◽

Hailong Jiao ◽

Pui-In Mak ◽

Rui P. Martins

Keyword(s):

Type I ◽

Reference Spur ◽

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A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction

Integration ◽

10.1016/j.vlsi.2021.12.007 ◽

2022 ◽

Author(s):

Rongjin Xu ◽

Dawei Ye ◽

C.-J. Richard Shi

Keyword(s):

Tracking Loop ◽

Frequency Tracking ◽

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Transmission Gate Based PFD Free of Glitches for Fast Locking PLL with Reduced Reference Spur

Communications in Computer and Information Science - Microelectronic Devices, Circuits and Systems ◽

10.1007/978-981-16-5048-2_32 ◽

2021 ◽

pp. 404-414

Author(s):

Radhika Singh ◽

K. K. Abdul Majeed ◽

Umakanta Nanda

Keyword(s):

Transmission Gate ◽

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A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter, -258.9 dB FOM and -65 dBc Reference Spur

2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) ◽

10.1109/rfic49505.2020.9218380 ◽

2020 ◽

Author(s):

Jiang Gong ◽

Fabio Sebastiano ◽

Edoardo Charbon ◽

Masoud Babaie

Keyword(s):

Reference Spur ◽

Charge Sampling

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A Spur-Frequency-Boosting PLL with a −74dBc reference-spur rejection in 90nm digital CMOS

2011 IEEE Radio Frequency Integrated Circuits Symposium ◽

10.1109/rfic.2011.5940706 ◽

2011 ◽

Author(s):

Mohamed Elsayed ◽

Mohammed Abdul-Latif ◽

Edgar Sanchez-Sinencio

Keyword(s):

Digital Cmos ◽

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A behavioral model of integer-N PLL frequency synthesizer for reference spur level simulation

2016 International Siberian Conference on Control and Communications (SIBCON) ◽

10.1109/sibcon.2016.7491738 ◽

2016 ◽

Author(s):

Denis I. Sotskov ◽

Vadim V. Elesin

Keyword(s):

Frequency Synthesizer ◽

Behavioral Model ◽

Reference Spur ◽

Pll Frequency Synthesizer

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