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Author(s):  
Junyi Qian ◽  
Yuanyuan Jiang ◽  
Zilong Zhang ◽  
Renyuan Zhang ◽  
Ziyu Wang ◽  
...  

2021 ◽  
Author(s):  
G. Srividhya ◽  
D. Kalaiyarasi ◽  
N. Pritha ◽  
S.L. Bharathi

Multiplications are the most important and crucial operation in any system. They are done through the process of repetitive addition. Since speed is necessary in any factor therefore multiplication must also be done in a faster way so that they are utilized properly for a faster result. This paper gives a detailed explanation on all three multipliers and compares them accordingly. In this paper, three various multiplication methods are considered and simulated. Three structural multipliers such as Vedic, Wallace tree and array multipliers are compared and their output is shown through the FGPA. For comparison, the results of multipliers are synthesized and simulated using XILINX.ISE.14.5 tool. Later the comparison is concluded by evaluating their utilization of the device.


2021 ◽  
Vol 11 (3) ◽  
pp. 49-52
Author(s):  
Anis Shahida Mokhtar ◽  
Nurlisa Zahari ◽  
Chew Sue Ping ◽  
Muhazam Mustapha ◽  
Norlaili Ismail ◽  
...  

2021 ◽  
Vol 1187 (1) ◽  
pp. 012003
Author(s):  
M Mummudi Murasu ◽  
Sanjana Sujith ◽  
A Anita Angeline ◽  
P. Sasi Priya ◽  
V S Kanchana Bhaaskaran

Author(s):  
Thammaneni Snehitha Reddy, Y. David Solomon Raju

The growth of computing resources and parallel computing has led to significant needs for efficient cryptosystems over the last decade. Elliptic Curve Cryptography (ECC) provides faster computation over other asymmetric cryptosystems such as RSA and greater security. For many cryptography operations, ECC can be used: hidden key exchange, message encryption, and digital signature. There is thus a trade-off between safety and efficiency with regard to speed, area and power requirements. This paper provides a good ECC approach to encryption by replacing the Vedic multiplier (16 bit) with the Wallace tree multiplier with an improved output (128 bit). The proposed design processes data recurringly with less volume, less power consumption and greater velocity, in addition to improving efficiency. Using Xilinx 2015.2 software, the entire proposed design is synthesized and simulated and implemented on the ZYNQ FPGA Board. Compared with previous implementations, a significant improvement in field efficiency, time complexity and energy demand is demonstrated by the proposed design.


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