scholarly journals Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1783 ◽  
Author(s):  
Ayaz Hussain ◽  
Muhammad Irfan ◽  
Naveed Khan Baloch ◽  
Umar Draz ◽  
Tariq Ali ◽  
...  
Keyword(s):  
Resource Sharing ◽  
Fault Tolerant ◽  
Single Chip ◽  
Protection Factor ◽  
Technology Scaling ◽  
Router Architecture ◽  
Permanent Faults ◽  
Multiple Paths ◽  
On Chip ◽  
The Cost

The router plays an important role in communication among different processing cores in on-chip networks. Technology scaling on one hand has enabled the designers to integrate multiple processing components on a single chip; on the other hand, it becomes the reason for faults. A generic router consists of the buffers and pipeline stages. A single fault may result in an undesirable situation of degraded performance or a whole chip may stop working. Therefore, it is necessary to provide permanent fault tolerance to all the components of the router. In this paper, we propose a mechanism that can tolerate permanent faults that occur in the router. We exploit the fault-tolerant techniques of resource sharing and paring between components for the input port unit and routing computation (RC) unit, the resource borrowing for virtual channel allocator (VA) and multiple paths for switch allocator (SA) and crossbar (XB). The experimental results and analysis show that the proposed mechanism enhances the reliability of the router architecture towards permanent faults at the cost of 29% area overhead. The proposed router architecture achieves the highest Silicon Protection Factor (SPF) metric, which is 24.8 as compared to the state-of-the-art fault-tolerant architectures. It incurs an increase in latency for SPLASH2 and PARSEC benchmark traffics, which is minimal as compared to the baseline router.

scholarly journals Protector: A Permanent Fault Resilient Router Architecture for Network on Chip

2020 ◽  
Vol 39 (4) ◽  
pp. 686-704
Author(s):  
Naveed Khan Baloch ◽  
Ayaz Hussain ◽  
Muhammad Iram Baig
Keyword(s):  
Network On Chip ◽  
Single Chip ◽  
Protection Factor ◽  
Permanent Fault ◽  
Baseline Design ◽  
Router Architecture ◽  
Multiple Paths ◽  
Undesirable Consequence ◽  
On Chip ◽  
Splash 2

The decreasing size of the transistor has increased the vulnerability towards faults. Increasing number of cores on a single chip has made the concept of Network on Chip (NoC) a standard communication backbone among cores. This facility comes with vulnerability of faults in the system due to decreasing size of transistors. A permanent fault in the network leads to undesirable consequence such as permanent blocking of flits or failure of the whole router. Preserving the router in the operational state has a significant impact on the reliability of the system. Permanent fault in buffers and pipeline stages of the router has a high impact on performance. The proposed router architecture Protector provides faults protection to both buffers and pipelines stages by exploiting the concepts of borrowing from other resources, using bypass paths and by creating multiple paths to reach output. The proposed router incurred an area overhead of 30% as compared to the baseline design. Reliability analysis using Silicon Protection Factor indicates that the proposed router has better fault tolerance efficiency as compared to state of the art. Latency analysis using PARSEC and SPLASH-2 benchmarks indicates proposed router incurs 13% and 16% latency overhead in the presence of faults.

scholarly journals NoCGuard: A Reliable Network-on-Chip Router Architecture

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 342 ◽  
Author(s):  
Muhammad Akmal Shafique ◽  
Naveed Khan Baloch ◽  
Muhammad Iram Baig ◽  
Fawad Hussain ◽  
Yousaf Bin Zikria ◽  
...  
Keyword(s):  
Network Architecture ◽  
Fault Tolerant ◽  
Channel Allocation ◽  
High Reliability ◽  
Low Cost ◽  
Network On Chip ◽  
Time To Failure ◽  
Protection Factor ◽  
Router Architecture ◽  
On Chip

Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.

Designing fault-tolerant network-on-chip router architecture

2010 ◽  
Vol 97 (10) ◽  
pp. 1181-1192 ◽  
Author(s):  
Ashkan Eghbal ◽  
Pooria M. Yaghini ◽  
H. Pedram ◽  
H. R. Zarandi
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Router Architecture ◽  
On Chip

scholarly journals Tolerating Permanent Faults in the Input Port of the Network on Chip Router

2019 ◽  
Vol 9 (1) ◽  
pp. 11 ◽  
Author(s):  
Hala Mohammed ◽  
Wameedh Flayyih ◽  
Fakhrul Rokhani
Keyword(s):  
Network Performance ◽  
Deep Submicron ◽  
Network On Chip ◽  
Input Port ◽  
Virtual Channel ◽  
Transient Faults ◽  
Single Chip ◽  
Permanent Faults ◽  
Hardware Redundancy ◽  
On Chip

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.

Providing fault tolerance through invasive computing

2016 ◽  
Vol 58 (6) ◽  
Author(s):  
Vahid Lari ◽  
Andreas Weichslgartner ◽  
Alexandru Tanase ◽  
Michael Witterauf ◽  
Faramarz Khosravi ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Fault Tolerant ◽  
Parallel Applications ◽  
Technology Scaling ◽  
The Face ◽  
Tightly Coupled ◽  
On Chip ◽  
Modular Redundancy ◽  
Parallel Arrays ◽  
Selection Of

AbstractAs a consequence of technology scaling, today's complex multi-processor systems have become more and more susceptible to errors. In order to satisfy reliability requirements, such systems require methods to detect and tolerate errors. This entails two major challenges: (a) providing a comprehensive approach that ensures fault-tolerant execution of parallel applications across different types of resources, and (b) optimizing resource usage in the face of dynamic fault probabilities or with varying fault tolerance needs of different applications. In this paper, we present a holistic and adaptive approach to provide fault tolerance on Multi-Processor System-on-a-Chip (MPSoC) on demand of an application or environmental needs based on invasive computing. We show how invasive computing may provide adaptive fault tolerance on a heterogeneous MPSoC including hardware accelerators and communication infrastructure such as a Network-on-Chip (NoC). In addition, we present (a) compile-time transformations to automatically adopt well-known redundancy schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) for fault-tolerant loop execution on a class of massively parallel arrays of processors called as Tightly Coupled Processor Arrays (). Based on timing characteristics derived from our compilation flow, we further develop (b) a reliability analysis guiding the selection of a suitable degree of fault tolerance. Finally, we present (c) a methodology to detect and adaptively mitigate faults in invasive NoCs.

scholarly journals Coherent spin qubit transport in silicon

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
J. Yoneda ◽  
W. Huang ◽  
M. Feng ◽  
C. H. Yang ◽  
K. W. Chan ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
High Fidelity ◽  
Nearest Neighbours ◽  
Quantum Processor ◽  
Spin Qubit ◽  
State Tomography ◽  
On Chip ◽  
The Cost ◽  
Silicon Based ◽  
The Impact

AbstractA fault-tolerant quantum processor may be configured using stationary qubits interacting only with their nearest neighbours, but at the cost of significant overheads in physical qubits per logical qubit. Such overheads could be reduced by coherently transporting qubits across the chip, allowing connectivity beyond immediate neighbours. Here we demonstrate high-fidelity coherent transport of an electron spin qubit between quantum dots in isotopically-enriched silicon. We observe qubit precession in the inter-site tunnelling regime and assess the impact of qubit transport using Ramsey interferometry and quantum state tomography techniques. We report a polarization transfer fidelity of 99.97% and an average coherent transfer fidelity of 99.4%. Our results provide key elements for high-fidelity, on-chip quantum information distribution, as long envisaged, reinforcing the scaling prospects of silicon-based spin qubits.

scholarly journals ENERGY AND POWER EFFICIENT SYSTEM ON CHIP WITH NANOSHEET FET

2019 ◽  
Vol 01 (01) ◽  
pp. 51-59 ◽  
Author(s):  
Mohan Kumar N.
Keyword(s):  
Power Dissipation ◽  
Cost Efficiency ◽  
Power Efficiency ◽  
System On Chip ◽  
Noise Tolerance ◽  
Single Chip ◽  
Efficient System ◽  
Power Efficient ◽  
On Chip ◽  
The Cost

As the level of integration of IC increases, System on Chip (SoC) design has evolved. This technology comprises of several intellectual property blocks on a single chip. With downsizing of transistors, the traditional elements used impose several challenges such as power dissipation, leakage and so on. These factors risk the cost efficiency of microsystems and risk the semiconductor industry’s capability to prolong Moore’s law in the nanometer range. This is overcome by the introduction of carbon materials such as nanosheet FET. They are advantageous over the traditional elements in terms of area and power efficiency. We design an energy and power efficient SoC with nanosheet FET that provides noise tolerance and memory optimization.

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