An Efficient 4X4 Mesh Structure with a Combination of Two NoC Router Architecture

Author(s):  
Vivek Tiwari ◽  
Kavita Khare ◽  
Smita Shandilya

: Network-on-Chip is used to integrate large numbers of Intellectual Property blocks on a single Integrated Chip. NoC router is one of the important parts of networking that is used inside a Chip. There are various topologies used in NoC network, mesh topology is one of them. In a conventional mesh structure, a defined NoC router is implemented at every node of the mesh structure. In this paper, a new 4x4 mesh structure is proposed and analyzed in which a combination of two different NoC router is implemented in a single mesh structure. Proposed mesh structure consists of one conventional NoC router and a new proposed NoC router which is designed in such a way that it can only transfer its input channel data into two output channel. To achieve this two-directional data transfer requirement, component of NoC router such as Crossbar switch, buffers are changed. This new proposed NoC router Architecture model is simulated in Xilinx ISE 9.2i and its targeted device is Virtex4. Where its area, power, is calculated. Then based on this result, an analysis for area and power is performed for Proposed 4x4 mesh structure. And this result analysis shows 17.24 % reduction in the area of proposed 4X4 mesh structure as compared to conventional 4X4 Mesh architecture. Further, this analysis also performed for 8x8, 16x16, 32x32 mesh structures. As the number of processors inside an SoC (System on a Chip) of a Mobile is increasing, the bus-based system can be replaced by an NoC system for better performance. The presented paper describes the effective utilization of NoC capabilities for next-generation mobile phones.

Author(s):  
Kamel Messaoudi ◽  
Salah Toumi ◽  
El-Bay Bourennane

Background: Network on chip is proposed as new reusable and scalable communication system for applications with important number of IPs. The NoC architecture characteristics are based on several factors: the implementation strategy of IPs, the power dissipation, the placement of IPs, data transfer time, the requirements of the given application, etc. The N×M Mesh topology combined with the XY routing algorithm are generally chosen in many studies. Hardware IPs proposed in the literature, for various applications as example video encoders, operates at different frequencies and generally implemented according to several strategies and different bus sizes. Connecting these IPs using the same communication system is very difficult. Methods: In this paper, we present a new topology based on multi-layer mesh topology and adapted for video coding applications. The proposed topology exploits the video coding information regarding groups of cores that communicate through two cores only. The idea is to use a specific NoC for each group of cores and connect the NoCs with bridge in the positions of two communication cores. The choice of parameters in each NoC depends on the characteristic of IPs in the same group in order to maximize communication adaptivity and performance. Results: Synthesis results show that the proposed multi-layer mesh topology NoC uses much less resources than the traditional NxM mesh topology NoC. Conclusion: This reduction in term of resources is assured by the considerable reduction in the length and number of global interconnects, resulting in an increase in the performance and decrease in the power consumption and area of wire limited circuits.


Author(s):  
А. Г. Гребеников ◽  
И. В. Малков ◽  
В. А. Урбанович ◽  
Н. И. Москаленко ◽  
Д. С. Колодийчик

The analysis of the design and technological features of the tail boom (ТB) of a helicopter made of polymer composite materials (PCM) is carried out.Three structural and technological concepts are distinguished - semi-monocoque (reinforced metal structure), monocoque (three-layer structure) and mesh-type structure. The high weight and economic efficiency of mesh structures is shown, which allows them to be used in aerospace engineering. The physicomechanical characteristics of the network structures are estimated and their uniqueness is shown. The use of mesh structures can reduce the weight of the product by a factor of two or more.The stress-strain state (SSS) of the proposed tail boom design is determined. The analysis of methods for calculating the characteristics of the total SSS of conical mesh shells is carried out. The design of the tail boom is presented, the design diagram of the tail boom of the transport category rotorcraft is developed. A finite element model was created using the Siemens NX 7.5 system. The calculation of the stress-strain state (SSS) of the HC of the helicopter was carried out on the basis of the developed structural scheme using the Advanced Simulation module of the Siemens NX 7.5 system. The main zones of probable fatigue failure of tail booms are determined. Finite Element Analysis (FEA) provides a theoretical basis for design decisions.Shown is the effect of the type of technological process selected for the production of the tail boom on the strength of the HB structure. The stability of the characteristics of the PCM tail boom largely depends on the extent to which its design is suitable for the use of mechanized and automated production processes.A method for the manufacture of a helicopter tail boom from PCM by the automated winding method is proposed. A variant of computer modeling of the tail boom of a mesh structure made of PCM is shown.The automated winding technology can be recommended for implementation in the design of the composite tail boom of the Mi-2 and Mi-8 helicopters.


2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang

Author(s):  
Xiaohan Tao ◽  
Jianmin Pang ◽  
Jinlong Xu ◽  
Yu Zhu

AbstractThe heterogeneous many-core architecture plays an important role in the fields of high-performance computing and scientific computing. It uses accelerator cores with on-chip memories to improve performance and reduce energy consumption. Scratchpad memory (SPM) is a kind of fast on-chip memory with lower energy consumption compared with a hardware cache. However, data transfer between SPM and off-chip memory can be managed only by a programmer or compiler. In this paper, we propose a compiler-directed multithreaded SPM data transfer model (MSDTM) to optimize the process of data transfer in a heterogeneous many-core architecture. We use compile-time analysis to classify data accesses, check dependences and determine the allocation of data transfer operations. We further present the data transfer performance model to derive the optimal granularity of data transfer and select the most profitable data transfer strategy. We implement the proposed MSDTM on the GCC complier and evaluate it on Sunway TaihuLight with selected test cases from benchmarks and scientific computing applications. The experimental result shows that the proposed MSDTM improves the application execution time by 5.49$$\times$$ × and achieves an energy saving of 5.16$$\times$$ × on average.


2017 ◽  
Vol 23 (3) ◽  
pp. 311-320 ◽  
Author(s):  
R.A.F. Oliveira ◽  
G.H. Justi ◽  
G.C. Lopes

In a cyclone design, pressure drop and collection efficiency are two important performance parameters to estimate its implementation viability. The optimum design provides higher efficiencies and lower pressure drops. In this paper, a grid independence study was performed to determine the most appropriate mesh to simulate the two-phase flow in a Stairmand cyclone. Computational fluid dynamic (CFD) tools were used to simulate the flow in an Eulerian-Lagrangian approach. Two different mesh structure, one with wall-refinement and the other with regular elements, and several mesh sizes were tested. The grid convergence index (GCI) method was applied to evaluate the result independence. The CFD model results were compared with empirical correlations from bibliography, showing good agreement. The wall-refined mesh with 287 thousand elements obtained errors of 9.8% for collection efficiency and 14.2% for pressure drop, while the same mesh, with regular elements, obtained errors of 8.7% for collection efficiency and 0.01% for pressure drop.


2019 ◽  
Author(s):  
Takuma Usuzaki ◽  
Minoru Shimoyama ◽  
Shuji Chiba ◽  
Naoko Mori

A medical test and accuracy of diagnosis are often discussed with contingency tables. However, it is difficult to apply a contingency table to multivariate cases because the number of possible categories increases exponentially. We hypothesize that randomly assigning Boolean operators and focusing on frequencies of Boolean operators could explain the outcome correctly, obtain the tendencies of operators, and overcome difficulties in analyzing large numbers of variables and categories. The aims of this paper are introducing a method to obtain tendencies of Boolean operators and expanding 2 by 2 contingency tables to multivariate cases. To test this method, we construct two types of data: 1) when variables and outcome were randomly determined and 2) when the outcome depends on one variable. Analysis of the first type of data by this method showed that there was no significant result. Analysis of the second type of data reflected the bias of the data. As far as we know, this is the first attempt to use a frequentist approach to randomly assigned Boolean operators.


2017 ◽  
Vol 17 (2) ◽  
pp. 73-82 ◽  
Author(s):  
Akash Punhani ◽  
Pardeep Kumar ◽  
Nitin Nitin

Abstract The performance of the interconnection network doesn’t only depend on the topology, but it also depends on the Routing algorithm used. The simplest Routing algorithm for the mesh topology in networks on chip is the XY Routing algorithm. The level based Routing algorithm has been proved to be more efficient than the XY Routing algorithm. In this paper, level based Routing algorithm using the dynamic programming has been proposed. The proposed Routing algorithm proves to be more efficient in the terms of the computation. The proposed Routing algorithm has achieved up to two times bigger speed.


2021 ◽  
Vol 20 (3) ◽  
pp. 1-6
Author(s):  
Mohammed Shaba Saliu ◽  
Muyideen Omuya Momoh ◽  
Pascal Uchenna Chinedu ◽  
Wilson Nwankwo ◽  
Aliu Daniel

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing.  By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low.  In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.


Sign in / Sign up

Export Citation Format

Share Document