Hardware efficient circuit for low error logarithmic converter

The need to implement high-speed Signal processing applications in which multiplication and division play a vital role made logarithmic arithmetic a prominent contender over the traditional arithmetic operations in recent years. But the logarithm and antilogarithm converters are the bottlenecks. In order to reduce the logarithmic conversion complexity, several works have been introduced from time to time for correcting the error in Mitchell’s algorithm but at the cost of hardware. In this work, we propose a 32-bit binary to the binary logarithmic converter with a simple correction circuit compared with existing techniques. Unlike the current methods that use the linear piece-wise approximation in the mantissa, we propose a weighted average method to correct the error in Mitchell’s approximation. The maximum error percentage from the proposed work is 0.91%, which is 16.9% of Mitchell’s error percentage.

Performance Improvement of Antilogarithmic Converter Using 28 Regions Error Correction Scheme

Logarithmic conversion is a significant portion of numerous digital signals processing system and other applications. The anti logarithmic transformation presented in this paper is able to support the anti logarithmic conversion of data with the number of bits up to thirty-two. An efficient FPGA hardware implementation of logarithmic operations is an alternative option used in arithmetic operations. In this paper, we implemented an efficient anti logarithmic converter using FPGA. This implementation is compared with 28 regions error correction scheme. The proposed hardware architecture having less area, delay with less error cost. This design is implemented using HDL tool and synthesized using Xilinx CAD tool. The implementation has with respect to existing antilog converter.