scholarly journals Performance Improvement of Antilogarithmic Converter Using 28 Regions Error Correction Scheme

2019 ◽  
Vol 8 (S3) ◽  
pp. 25-29
Author(s):  
A. T. A. Kishore Kumar ◽  
R. Seshasayanan
Keyword(s):  
Error Correction ◽  
Performance Improvement ◽  
Hardware Implementation ◽  
Processing System ◽  
Hardware Architecture ◽  
Digital Signals ◽  
Correction Scheme ◽  
Error Cost ◽  
Cad Tool ◽  
Logarithmic Converter

Logarithmic conversion is a significant portion of numerous digital signals processing system and other applications. The anti logarithmic transformation presented in this paper is able to support the anti logarithmic conversion of data with the number of bits up to thirty-two. An efficient FPGA hardware implementation of logarithmic operations is an alternative option used in arithmetic operations. In this paper, we implemented an efficient anti logarithmic converter using FPGA. This implementation is compared with 28 regions error correction scheme. The proposed hardware architecture having less area, delay with less error cost. This design is implemented using HDL tool and synthesized using Xilinx CAD tool. The implementation has with respect to existing antilog converter.

Hardware architecture of OFCE-HS for hardware implementation

2011 ◽  
Author(s):  
Ruzali Rustam ◽  
Nor Hisham Hamid ◽  
Fawnizu Azmadi Hussin
Keyword(s):  
Hardware Implementation ◽  
Hardware Architecture

scholarly journals Efficient error correcting scheme for chaos shift keying signals

2019 ◽  
Vol 9 (5) ◽  
pp. 3550
Author(s):  
Hikmat N. Abdullah ◽  
Thamir R. Saeed ◽  
Asaad H. Sahar
Keyword(s):  
Error Correction ◽  
Logistic Map ◽  
Chaotic Sequence ◽  
Chaos Communication ◽  
Shortest Distance ◽  
Correction Scheme ◽  
Shift Keying ◽  
Minimum Delay ◽  
Modified Logistic Map ◽  
Chaos Shift Keying

An effective error-correction scheme based on normalized correlation for a non coherent chaos communication system with no redundancy bits is proposed in this paper. A modified logistic map is used in the proposed scheme for generating two sequences, one for every data bit value, in a manner that the initial value of the next chaotic sequence is set by the second value of the present chaotic sequence of the similar symbol. This arrangement, thus, has the creation of successive chaotic sequences with identical chaotic dynamics for error correction purpose. The detection symbol is performed prior to correction, on the basis of the suboptimal receiver which anchors on the computation of the shortest distance existing between the received sequence and the modified logistic map’s chaotic trajectory. The results of the simulation reveal noticeable Eb/No improvement by the proposed scheme over the prior to the error- correcting scheme with the improvement increasing whenever there is increase in the number of sequence N. Prior to the error-correcting scheme when N=8, a gain of 1.3 dB is accomplished in E<sub>b</sub>/N<sub>o</sub> at 10<sup>-3 </sup>bit error probability. On the basis of normalized correlation, the most efficient point in our proposed error correction scheme is the absence of any redundant bits needed with minimum delay procedure, in contrast to earlier method that was based on suboptimal method detection and correction. Such performance would render the scheme good candidate for applications requiring high rates of data transmission.

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