linear chirp
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Measurement ◽  
2021 ◽  
pp. 109635
Author(s):  
Antonio Moschitta ◽  
Antonella Comuniello ◽  
Alessio De Angelis ◽  
Francesco Santoni ◽  
Paolo Carbone

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Mahmoud M. A. Eid ◽  
Ahmed Helmy ◽  
Ahmed Nabih Zaki Rashed

Abstract Linear/Measured chirped Gaussian pulse propagation is simulated at various data rates transmission in the presence of group velocity dispersion without amplification unit. The power variations (PVs) vs. frequency, time period are also clarified after 250 km fiber channel length and 10 Gb/s bit rate (BR) of for Gaussian pulse generators with linear chirp factor of 2 rad/s, measured chirp factor (alpha parameter of 2 rad/W, Adiabatic chirp of 10 s−1). Moreover the overall total light power after fiber, the overall total electrical power after APD receiver are studied and clarified for Gaussian pulse generators with linear chirp, measured chirp factor. PVs vs. frequency, time period are simulated after APD receiver for Gaussian pulse generators with linear chirp, measured chirp factor. Maximum signal amplitude variations vs. time after APD receiver for Gaussian pulse generators with linear chirp, measured chirp factor are also clarified with the numerical simulation results.


Author(s):  
Antonio Moschitta ◽  
Antonella Comuniello ◽  
Francesco Santoni ◽  
Alessio De Angelis ◽  
Paolo Carbone ◽  
...  

2020 ◽  
Vol 60 (6) ◽  
Author(s):  
Jan Kunz ◽  
Petr Beneš

This paper deals with a logarithmic and a linear chirp sine generation on a fixed-point FPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basic overview of the logarithmic chirp sine signal is provided. Then, methods of software signal generation as well as different hardware platforms are briefly described and their pros and cons are mentioned. A DDS generator on FPGA needs the phase difference between samples as an input. This generation for the logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-point arithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and is able to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of 1 oct/min.


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