TSCache

Time-series databases are becoming an indispensable component in today's data centers. In order to manage the rapidly growing time-series data, we need an effective and efficient system solution to handle the huge traffic of time-series data queries. A promising solution is to deploy a high-speed, large-capacity cache system to relieve the burden on the backend time-series databases and accelerate query processing. However, time-series data is drastically different from other traditional data workloads, bringing both challenges and opportunities. In this paper, we present a flash-based cache system design for time-series data, called TSCache . By exploiting the unique properties of time-series data, we have developed a set of optimization schemes, such as a slab-based data management, a two-layered data indexing structure, an adaptive time-aware caching policy, and a low-cost compaction process. We have implemented a prototype based on Twitter's Fatcache. Our experimental results show that TSCache can significantly improve client query performance, effectively increasing the bandwidth by a factor of up to 6.7 and reducing the latency by up to 84.2%.

Cache filtering algorithm for least frequently used data with accurate memory simulation

We propose a cache filtering algorithm to improve processor performance using a small buffer inside the processor and an algorithm to filter least frequently used accesses from Ll and L2 caches. The algorithm uses simple DRAM fast-page accessing mode to identity accesses that are not previously accessed or not frequently used and keep them out of the cache system and store them in small buffer. We have also added a realistic page interleaved DDR3 memory simulation model to the SimpleScalar simulator. This model supports any processor and memory clock speeds, different sets of memory latencies, various configurations of memory banks and channels. Results show that the filtering algorithm could improve· performance of some applications compared to the same system that does not use the filtering algorithm

Cache filtering algorithm for least frequently used data with accurate memory simulation

We propose a cache filtering algorithm to improve processor performance using a small buffer inside the processor and an algorithm to filter least frequently used accesses from Ll and L2 caches. The algorithm uses simple DRAM fast-page accessing mode to identity accesses that are not previously accessed or not frequently used and keep them out of the cache system and store them in small buffer. We have also added a realistic page interleaved DDR3 memory simulation model to the SimpleScalar simulator. This model supports any processor and memory clock speeds, different sets of memory latencies, various configurations of memory banks and channels. Results show that the filtering algorithm could improve· performance of some applications compared to the same system that does not use the filtering algorithm

An Incrementally Deployable IP-Compatible-Information-Centric Networking Hierarchical Cache System

The major advantage of information-centric networking (ICN) lies in in-network caching. Ubiquitous cache nodes reduce the user’s download latency of content and the drain of network bandwidth, which enables efficient content distribution. Due to the huge cost of updating an entire network infrastructure, it is realistic for ICN to be integrated into an IP network, which poses new challenges to design a cache system and corresponding content router. In this paper, we firstly observed that the behavior pattern of data requests based on a name resolution system (NRS) makes an ICN cache system implicitly form a hierarchical and nested structure. We propose a complete design and an analytical model to characterize an uncooperative hierarchical ICN caching system compatible with IP. Secondly, to facilitate the incremental deployment of an ICN cache system in an IP network, we designed and implemented a cache-supported router with multi-terabyte cache capabilities. Finally, the simulation and measurement results show the accuracy of proposed analytical model, the significant gains on hit ratio, and the access latency of the hierarchical ICN cache system compared with a flat cache system based on naming routing, as well as the high performance of the implemented ICN router.

File Type and Access Pattern Aware Buffer Cache Management for Rendering Systems

Rendering is the process of generating high-resolution images by software, which is widely used in animation, video games and visual effects in movies. Although rendering is a computation-intensive job, we observe that storage accesses may become another performance bottleneck in desktop-rendering systems. In this article, we present a new buffer cache management scheme specialized for rendering systems. Unlike general-purpose computing systems, rendering systems exhibit specific file access patterns, and we show that this results in significant performance degradation in the buffer cache system. To cope with this situation, we collect various file input/output (I/O) traces of rendering workloads and analyze their access patterns. The results of this analysis show that file I/Os in rendering processes consist of long loops for configuration, short loops for texture input, random reads for input, and single-writes for output. Based on this observation, we propose a new buffer cache management scheme for improving the storage performance of rendering systems. Experimental results show that the proposed scheme improves the storage I/O performance by an average of 19% and a maximum of 55% compared to the conventional buffer cache system.