Data-Loop-Free Self-Timed Circuit Verification

2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) ◽

10.1109/async.2018.00023 ◽

2018 ◽

Author(s):

Cuong Chau ◽

Warren Hunt ◽

Matt Kaufmann ◽

Marly Roncken ◽

Ivan Sutherland

Keyword(s):

Circuit Verification

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Multipliers and dividers: Insights on arithmetic circuit verification (extended abstract)

Computer Aided Verification - Lecture Notes in Computer Science ◽

10.1007/3-540-60045-0_35 ◽

1995 ◽

pp. 1-3

Author(s):

Randal E. Bryant

Keyword(s):

Arithmetic Circuit ◽

Circuit Verification

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Integrating SMT with Theorem Proving for Analog/Mixed-Signal Circuit Verification

Lecture Notes in Computer Science - NASA Formal Methods ◽

10.1007/978-3-319-17524-9_22 ◽

2015 ◽

pp. 310-326 ◽

Author(s):

Yan Peng ◽

Mark Greenstreet

Keyword(s):

Theorem Proving ◽

Mixed Signal ◽

Circuit Verification

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Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Lecture Notes in Computer Science ◽

10.1007/978-3-642-17752-1_19 ◽

2011 ◽

pp. 190-199

Author(s):

Qin Tang ◽

Amir Zjajo ◽

Michel Berkelaar ◽

Nick van der Meijs

Keyword(s):

Process Variations ◽

Cmos Circuit ◽

Statistical Process ◽

Circuit Verification

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A Hierarchical Approach to Self-Timed Circuit Verification

2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) ◽

10.1109/async.2019.00022 ◽

2019 ◽

Author(s):

Cuong Chau ◽

Warren A. Hunt ◽

Matt Kaufmann ◽

Marly Roncken ◽

Ivan Sutherland

Keyword(s):

Hierarchical Approach ◽

Circuit Verification

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Sequential circuit verification using symbolic model checking

27th ACM/IEEE Design Automation Conference ◽

10.1145/123186.123223 ◽

1990 ◽

Author(s):

J. R. Burch ◽

E. M. Clarke ◽

K. L. McMillan ◽

David L. Dill

Keyword(s):

Model Checking ◽

Symbolic Model Checking ◽

Sequential Circuit ◽

Symbolic Model ◽

Circuit Verification

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Formal approaches to analog circuit verification

2009 Design, Automation & Test in Europe Conference & Exhibition ◽

10.1109/date.2009.5090759 ◽

2009 ◽

Author(s):

E. Barke ◽

D. Grabowski ◽

H. Graeb ◽

L. Hedrich ◽

S. Heinen ◽

...

Keyword(s):

Analog Circuit ◽

Circuit Verification

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*PHDD: an efficient graph representation for floating point circuit verification

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97 ◽

10.1109/iccad.1997.643251 ◽

1997 ◽

Author(s):

Yimg-An Chen ◽

Bryant

Keyword(s):

Graph Representation ◽

Floating Point ◽

Circuit Verification

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Symbolic model checking for sequential circuit verification

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.275352 ◽

1994 ◽

Vol 13 (4) ◽

pp. 401-424 ◽

Author(s):

J.R. Burch ◽

E.M. Clarke ◽

D.E. Long ◽

K.L. McMillan ◽

D.L. Dill

Keyword(s):

Model Checking ◽

Symbolic Model Checking ◽

Sequential Circuit ◽

Symbolic Model ◽

Circuit Verification

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On the impact of structural circuit partitioning on SAT-based combinational circuit verification

Fifth International Workshop on Microprocessor Test and Verification (MTV 04) MTV-05 ◽

10.1109/mtv.2004.18 ◽

2006 ◽

Author(s):

M. Herbstritt ◽

T. Kmieciak ◽

B. Becker

Keyword(s):

Circuit Partitioning ◽

Combinational Circuit ◽

Circuit Verification ◽

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Expiratory Valve Dysfunction in a Semiclosed Circle Anesthesia Circuit???Verification by Analysis of Carbon Dioxide Waveform

Anesthesia & Analgesia ◽

10.1213/00000539-198405000-00014 ◽

1984 ◽

Vol 63 (5) ◽

pp. 536???537 ◽

Author(s):

Stephen T. Pyles ◽

Lawrence S. Berman ◽

Jerome H. Modell

Keyword(s):

Carbon Dioxide ◽

Valve Dysfunction ◽

Expiratory Valve ◽

Circuit Verification

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