Modified Hermite integrators of arbitrary order

ABSTRACT We present a family of modified Hermite integrators of arbitrary order possessing superior behaviour for the integration of Keplerian and near-Keplerian orbits. After recounting the derivation of Hermite N-body integrators of arbitrary order, we derive a corrector expression that minimizes integrated errors in the argument of periapsis for any such integrator. In addition to providing an alternate derivation of the modified corrector for the fourth-order Hermite integrator, we focus on improved correctors for the sixth- and eighth-order integrators previously featured in the literature. We present a set of numerical examples and find that the higher order schemes improve performance, even when considering their slightly higher cost in floating point operations. The algorithms presented herein hold promise for systems dominated by central potentials, such as planetary systems and the centres of galaxies. Existing Hermite integrators of any order can be modified to use the expressions presented here with minimal effort. Accordingly, the schemes presented herein can be easily implemented on massively parallel architectures.

A Preconditioned Iterative Approach for Efficient Full Chip Thermal Analysis on Massively Parallel Platforms

Efficient full-chip thermal simulation is among the most challenging problems facing the EDA industry today, especially for modern 3D integrated circuits, due to the huge linear systems resulting from thermal modeling approaches that require unreasonably long computational times. While the formulation problem, by applying a thermal equivalent circuit, is prevalent and can be easily constructed, the corresponding 3D equations network has an undesirable time-consuming numerical simulation. Direct linear solvers are not capable of handling such huge problems, and iterative methods are the only feasible approach. In this paper, we propose a computationally-efficient iterative method with a parallel preconditioned technique that exploits the resources of massively-parallel architectures such as Graphic Processor Units (GPUs). Experimental results demonstrate that the proposed method achieves a speedup of 2.2× in CPU execution and a 26.93× speedup in GPU execution over the state-of-the-art iterative method.

Trends and Challenges in Large-Scale HPC Network Analysis

Many algorithms in graph analytics can be sped up by using the power of low-cost but massively parallel architectures, such as GPUs. On the other hand, the storage and analysis capabilities needed for large-scale graph analytics have motivated the development of a new wave of HPC technologies, including MapReduce-like BSP distributed analytics, No-SQL data storage and querying, and homogeneous and hybrid multi-core/GPU graph supercomputing. In this chapter, the authors review these trends and current challenges for HPC large-scale graph analysis.