2010 International Conference on Field Programmable Logic and Applications
Latest Publications

TOTAL DOCUMENTS

124

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H-INDEX

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Published By IEEE

9781424478422, 9781424478439

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems

2010 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2010.13 ◽

2010 ◽

Cited By ~ 6

Author(s):

Salvatore Pontarelli ◽

Claudio Greco ◽

Enrico Nobile ◽

Simone Teofili ◽

Giuseppe Bianchi

Keyword(s):

Intrusion Detection ◽

Dynamic Reconfiguration ◽

Intrusion Detection Systems ◽

Network Intrusion Detection ◽

Detection Systems ◽

Network Intrusion ◽

Network Intrusion Detection Systems

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Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic

2010 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2010.15 ◽

2010 ◽

Cited By ~ 3

Author(s):

Amit Verma ◽

Ajay K. Verma ◽

Hadi Parandeh-Afshar ◽

Philip Brisk ◽

Paolo Ienne

Keyword(s):

Floating Point

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GPU Versus FPGA for High Productivity Computing

2010 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2010.32 ◽

2010 ◽

Cited By ~ 29

Author(s):

David H. Jones ◽

Adam Powell ◽

Christos-Savvas Bouganis ◽

Peter Y.K. Cheung

Keyword(s):

High Productivity

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Real-Time Processing of Contrast Limited Adaptive Histogram Equalization on FPGA

2010 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2010.37 ◽

2010 ◽

Cited By ~ 15

Author(s):

Kentaro Kokufuta ◽

Tsutomu Maruyama

Keyword(s):

Real Time ◽

Histogram Equalization ◽

Real Time Processing ◽

Time Processing ◽

Adaptive Histogram Equalization

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Customized Exposed Datapath Soft-Core Design Flow with Compiler Support

2010 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2010.51 ◽

2010 ◽

Cited By ~ 53

Author(s):

Otto Esko ◽

Pekka Jaaskelainen ◽

Pablo Huerta ◽

Carlos S. de La Lama ◽

Jarmo Takala ◽

...

Keyword(s):

Design Flow ◽

Soft Core ◽

Compiler Support

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Test Compression for Dynamically Reconfigurable Processors

2010 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2010.49 ◽

2010 ◽

Author(s):

Hiroaki Inoue ◽

Junya Yamada ◽

Hideyuki Yoneda ◽

Katsumi Togawa ◽

Koichiro Furuta

Keyword(s):

Dynamically Reconfigurable ◽

Test Compression ◽

Reconfigurable Processors

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Generation of Deterministic MCU/FPGA Hybrid Systems from UML Activities

2010 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2010.74 ◽

2010 ◽

Cited By ~ 1

Author(s):

Ruediger Willenberg ◽

Zamira Daw ◽

Christian Englert ◽

Marcus Vetter

Keyword(s):

Hybrid Systems

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Sum of Absolute Difference Implementations for Image Processing on FPGAs

2010 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2010.40 ◽

2010 ◽

Cited By ~ 7

Author(s):

Hiroaki Niitsuma ◽

Tsutomu Maruyama

Keyword(s):

Image Processing ◽

Absolute Difference

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FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers

2010 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2010.25 ◽

2010 ◽

Cited By ~ 22

Author(s):

David B. Thomas ◽

Wayne Luk

Keyword(s):

Random Number ◽

Random Number Generators ◽

Uniform Random Number

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Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine

2010 International Conference on Field Programmable Logic and Applications ◽

10.1109/fpl.2010.39 ◽

2010 ◽

Cited By ~ 2

Author(s):

Stephen Wray ◽

Wayne Luk ◽

Peter Pietzuch

Keyword(s):

Algorithmic Trading ◽

Run Time ◽

Run Time Reconfiguration

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2010 International Conference on Field Programmable Logic and ApplicationsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic

GPU Versus FPGA for High Productivity Computing

Real-Time Processing of Contrast Limited Adaptive Histogram Equalization on FPGA

Customized Exposed Datapath Soft-Core Design Flow with Compiler Support

Test Compression for Dynamically Reconfigurable Processors

Generation of Deterministic MCU/FPGA Hybrid Systems from UML Activities

Sum of Absolute Difference Implementations for Image Processing on FPGAs

FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers

Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine

2010 International Conference on Field Programmable Logic and Applications
Latest Publications