reconfigurable devices
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Author(s):  
Liang He ◽  
Jarrid A. Wittkopf ◽  
Ji Won Jun ◽  
Kris Erickson ◽  
Rafael Tico Ballagas

Integrating electronics with highly custom 3D designs for the physical fabrication of interactive prototypes is traditionally cumbersome and requires numerous iterations of manual assembly and debugging. With the new capabilities of 3D printers, combining electronic design and 3D modeling workflows can lower the barrier for achieving interactive functionality or iterating on the overall design. We present ModElec---an interactive design tool that enables the coordinated expression of electronic and physical design intent by allowing designers to integrate 3D-printable circuits with 3D forms. With ModElec, the user can arrange electronic parts in a 3D body, modify the model design with embedded circuits updated, and preview the auto-generated 3D traces that can be directly printed with a multi-material-based 3D printer. We demonstrate the potential of ModElec with four example applications, from a set of game controls to reconfigurable devices. Further, the tool was reported as easy to use through a preliminary evaluation with eight designers.


Electronics ◽  
2021 ◽  
Vol 10 (24) ◽  
pp. 3072
Author(s):  
Rodrigo Ribeiro de Oliveira ◽  
Felipe Augusto Souza Guimarães ◽  
Mateus Martínez de Lucena ◽  
Lucas Carvalho Cordeiro ◽  
Eddie Batista de Lima Filho ◽  
...  

This paper presents a new hardware reconfiguration approach named hardware reconfiguration through digital television (HARD), which can update FPGA hardware modules based on digital TV (DTV) signals. Such a scheme allows several synthesized hardware cores (bitstreams) signaled and broadcast through open DTV signals via data streaming to be identified, acquired, decoded, and then used for system updates. Reconfiguration data are partitioned, encapsulated into private sections, and then sent in a carrousel fashion in order to be recovered by modified receivers. Service information content, specially designed for identifying and describing the characteristics of multiplexed hardware bitstreams, was added to the transmitted signal and provided all necessary information in the traditional DTV style. The receiver framework, in turn, checked whether those characteristics corresponded to its embedded reconfigurable devices and, if a match was found, it reassembled the related bitstreams and reconfigured the respective internal circuits. Experiments performed with an implementation of the proposed methodology confirmed its feasibility and showed that remounting and reconfiguration times were satisfactory and presented no blocking aspect. Finally, HARD can be used in several designs regarding intelligent reconfigurable devices, minimize device costs in the long term, and provide better hardware reuse.


2021 ◽  
Author(s):  
Fernando Moreno ◽  
Yael Gutierrez Vela ◽  
Gonzalo Santos ◽  
Pablo García-Fernández ◽  
Javier Junquera ◽  
...  

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Francesco Morichetti ◽  
Maziyar Milanizadeh ◽  
Matteo Petrini ◽  
Francesco Zanetto ◽  
Giorgio Ferrari ◽  
...  

AbstractFlexible optical networks require reconfigurable devices with operation on a wavelength range of several tens of nanometers, hitless tuneability (i.e. transparency to other channels during reconfiguration), and polarization independence. All these requirements have not been achieved yet in a single photonic integrated device and this is the reason why the potential of integrated photonics is still largely unexploited in the nodes of optical communication networks. Here we report on a fully-reconfigurable add-drop silicon photonic filter, which can be tuned well beyond the extended C-band (almost 100 nm) in a complete hitless (>35 dB channel isolation) and polarization transparent (1.2 dB polarization dependent loss) way. This achievement is the result of blended strategies applied to the design, calibration, tuning and control of the device. Transmission quality assessment on dual polarization 100 Gbit/s (QPSK) and 200 Gbit/s (16-QAM) signals demonstrates the suitability for dynamic bandwidth allocation in core networks, backhaul networks, intra- and inter-datacenter interconnects.


2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Conner Ballew ◽  
Gregory Roberts ◽  
Sarah Camayd-Muñoz ◽  
Maximilien F. Debbas ◽  
Andrei Faraon

AbstractMetasurfaces advanced the field of optics by reducing the thickness of optical components and merging multiple functionalities into a single layer device. However, this generally comes with a reduction in performance, especially for multi-functional and broadband applications. Three-dimensional metastructures can provide the necessary degrees of freedom for advanced applications, while maintaining minimal thickness. This work explores mechanically reconfigurable devices that perform focusing, spectral demultiplexing, and polarization sorting based on mechanical configuration. As proof of concept, a rotatable device, a device based on rotating squares, and a shearing-based device are designed with adjoint-based topology optimization, 3D-printed, and measured at microwave frequencies (7.6–11.6 GHz) in an anechoic chamber.


Author(s):  
Arief Wicaksana ◽  
Olivier Muller ◽  
Frédéric Rousseau ◽  
Arif Sasongko

2021 ◽  
Author(s):  
Francesco Morichetti ◽  
Maziyar Milanizadeh ◽  
Matteo Petrini ◽  
Francesco Zanetto ◽  
Giorgio Ferrari ◽  
...  

Abstract Flexible optical networks require reconfigurable devices with operation on a wavelength range of several tens of nanometers, hitless tuneability (i.e. transparency to other channels during reconfiguration), and polarization independence. All these requirements have not been achieved yet in a single photonic integrated device and this is the reason why the potential of integrated photonics is still largely unexploited in the nodes of optical communication networks. Here we report on a fully-reconfigurable add-drop silicon photonic filter, which can be tuned well beyond the extended C-band (almost 100 nm) in a complete hitless (>35 dB channel isolation) and polarization transparent (1.2 dB polarization dependent loss) way. This achievement is the result of blended strategies applied to the design, calibration, tuning and control of the device. Transmission quality assessment on dual polarization 100 Gbit/s (QPSK) and 200 Gbit/s (16-QAM) signals demonstrate the suitability for dynamic bandwidth allocation in core networks, back-haul networks, intra- and inter-datacenter interconnects.


2021 ◽  
Vol 21 (1) ◽  
pp. 64-70
Author(s):  
Jeong Hun Park ◽  
Moon-Que Lee

This paper presents a new dual-band diode mixer for the X- and K-bands. The proposed mixer consists of a pair of series-connected diodes and a frequency-dependent delay line that operates at 180° and 360° at the X-band of 10.525 GHz and at the K-band of 24.15 GHz, respectively. Without reconfigurable devices such as switches, the proposed mixer operates as a single-balanced diode mixer at the X-band and a subharmonically pumped antiparallel diode mixer at the K-band simultaneously. The designed circuit was implemented in a hybrid microwave integrated circuit using discretely packaged RF components on a microwave printed circuit board. The measurement results showed conversion losses of 6.5 dB and 16.6 dB at the X- and K-bands, respectively.


Author(s):  
А.А. Пирогов ◽  
Ю.А. Пирогова ◽  
С.А. Гвозденко ◽  
Д.В. Шардаков ◽  
Б.И. Жилин

Цифровая фильтрация распознаваемых сигналов является непременной процедурой при обнаружении и распознавании сообщений. Под фильтрацией понимают любое преобразование сигналов, при котором во входной последовательности обрабатываемых данных целенаправленно изменяются определенные соотношения между различными параметрами сигналов. Системы, избирательно меняющие форму сигналов, устраняющие или уменьшающие помехи, извлекающие из сигналов определенную информацию и т.п., называют фильтрами. Соответственно, фильтры с любым целевым назначением являются частным случаем систем преобразования сигналов. Программируемые логические интегральные схемы (ПЛИС) представляют собой конфигурируемые интегральные схемы, логика работы которых определяется посредством их программирования. Применение ПЛИС для задач цифровой обработки сигналов позволяет получать устройства, способные менять конфигурацию, подстраиваться под определенную задачу за счет их гибко изменяемой, программируемой структуры. При разработке сложных устройств могут применяться в качестве компонентов для проектирования готовые блоки - IP-ядра или сложно-функциональные блоки (СФ-блоки). Использование программных СФ-блоков позволяет наиболее эффективно задействовать их в конечной структуре, в значительной степени сократить затраты на проектирование. Цель работы состоит в построении RTL модели СФ-блока цифровой обработки сигналов, его верификации как на логическом уровне, так и физическом Digital filtering of recognized signals is an indispensable procedure for the detection and recognition of messages. Filtering is understood as any transformation of signals in which certain relationships between different signal parameters are purposefully changed in the input sequence of the processed data. Systems that selectively change the shape of signals, eliminate or reduce interference, extract certain information from the signals, and so on, are called filters. Accordingly, filters with any purpose are a special case of signal conversion systems. Programmable logic integrated circuits (FPGAs) are configurable integrated circuits whose logic is defined through programming. The use of FPGAs for digital signal processing tasks makes it possible to obtain devices capable of changing the configuration, adapting to a specific task due to their flexibly changeable, programmable structure. When developing complex devices, ready-made blocks - IP-cores or complex-functional blocks (SF blocks) - can be used as components for design. The use of software SF-blocks allows them to be used most effectively in the final structure, to a significant extent to reduce design costs. The purpose of the work is to build an RTL model of the SF-block for digital signal processing, its verification both at the logical and physical levels


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