2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)
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Fermi level pinning at the polySi/metal oxide interface

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221060 ◽

2004 ◽

Cited By ~ 29

Author(s):

C. Hobbs ◽

L. Fonseca ◽

V. Dhandapani ◽

S. Samavedam ◽

B. Taylor ◽

...

Keyword(s):

Metal Oxide ◽

Fermi Level ◽

Oxide Interface ◽

Fermi Level Pinning

High performance 25 nm FDSOI devices with extremely thin silicon channel

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221120 ◽

2004 ◽

Cited By ~ 6

Author(s):

Z. Krivokapic ◽

W. Maszara ◽

F. Arasnia ◽

E. Paton ◽

Y. Kim ◽

...

Keyword(s):

High Performance ◽

Thin Silicon

Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65 nm mode low power CMOS applications

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221064 ◽

2004 ◽

Cited By ~ 10

Author(s):

S. Inumiya ◽

K. Sekine ◽

S. Niwa ◽

A. Kaneko ◽

M. Sato ◽

...

Keyword(s):

Low Power ◽

Gate Dielectrics ◽

Plasma Oxidation ◽

Low Power Cmos

Highly manufacturable SONOS non-volatile memory for the embedded SoC solution

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221071 ◽

2004 ◽

Cited By ~ 6

Author(s):

J.-H. Kim ◽

I.W. Cho ◽

G.J. Bae ◽

S.S. Kim ◽

K.C. Kim ◽

...

Keyword(s):

Non Volatile Memory ◽

Volatile Memory ◽

Embedded Soc

Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221084 ◽

2004 ◽

Author(s):

Jaegoo Lee ◽

Yongseok Ahn ◽

Yangkeun Park ◽

Minsang Kim ◽

Dongjun Lee ◽

...

Keyword(s):

High Performance ◽

Memory Cell ◽

Storage Node

FBC (Floating Body Cell) for embedded DRAM on SOI

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221087 ◽

2004 ◽

Cited By ~ 26

Author(s):

K. Inoh ◽

T. Shino ◽

H. Yamada ◽

H. Nakajima ◽

Y. Minami ◽

...

Keyword(s):

Floating Body ◽

Body Cell

A new Si:C epitaxial channel nMOSFET architecture with improved drivability and short-channel characteristics

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221081 ◽

2004 ◽

Cited By ~ 8

Author(s):

T. Ernst ◽

F. Ducroquet ◽

J.-M. Hartmann ◽

O. Weber ◽

V. Loup ◽

...

Keyword(s):

Short Channel ◽

Channel Characteristics

Impact of oxygen-enriched SiN interface on Al/sub 2/O/sub 3/ gate stack. An innovative solution to low-power CMOS

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221127 ◽

2004 ◽

Author(s):

S. Saito ◽

Y. Shimamoto ◽

S. Tsujikawa ◽

H. Hamamura ◽

O. Tonomura ◽

...

Keyword(s):

Low Power ◽

Gate Stack ◽

Innovative Solution ◽

Low Power Cmos

Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221069 ◽

2004 ◽

Cited By ~ 27

Author(s):

T. Sugizaki ◽

M. Kobayashi ◽

M. Ishidao ◽

H. Minakata ◽

M. Yamaguchi ◽

...

Keyword(s):

Flash Memory ◽

Charge Trapping ◽

High K

Very low defects and high performance Ge-on-insulator p-MOSFETs with Al/sub 2/O/sub 3/ gate dielectrics

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221114 ◽

2004 ◽

Cited By ~ 8

Author(s):

C.H. Huang ◽

M.Y. Yang ◽

Albert Chin ◽

W.J. Chen ◽

C.X. Zhu ◽

...

Keyword(s):

High Performance ◽

Gate Dielectrics

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Fermi level pinning at the polySi/metal oxide interface

High performance 25 nm FDSOI devices with extremely thin silicon channel

Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65 nm mode low power CMOS applications

Highly manufacturable SONOS non-volatile memory for the embedded SoC solution

Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond

FBC (Floating Body Cell) for embedded DRAM on SOI

A new Si:C epitaxial channel nMOSFET architecture with improved drivability and short-channel characteristics

Impact of oxygen-enriched SiN interface on Al/sub 2/O/sub 3/ gate stack. An innovative solution to low-power CMOS

Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

Very low defects and high performance Ge-on-insulator p-MOSFETs with Al/sub 2/O/sub 3/ gate dielectrics

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)
Latest Publications