CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

Design of Low Power Less Leakage Quarternary Adder Using CMOS

In VLSI, design and implementation of circuits with MOS devices and binary logic are quite usual. The Main Objective is to design a low power and minimum leakage Quaternary adder. The VLSI field consists of Multi-valued logic (MVL) such as ternary and Quaternary Logic (QTL). The Failures such as Short Channel Effects (SCE) Impact-ionization and surface scattering are in normalized aspects. The Quaternary radix on MVL (multi-valued logic) monitors and reduces the area. The Quaternary (four-valued) logic converts the quaternary signals and binary signals produced by the by the existing binary circuits. The Proposed is carried out with LTSPICE tool and CMOS technology.

Simulation of the characteristics of low-voltage gates on combined cylindrical surrounding gate field-effect nanotransistors

The applicability of the architecture of a nanoscale surrounding gate field-effect transistor with a combined cylindrical working area for low-voltage applications is discussed. At the same time, the licensed TCAD Sentaurus instrument and technological modeling system is used as a tool. The transistor architecture under consideration involves combining the working zones of n-channel and p-channel transistors with one common gate. At the same time, the efficiency of suppressing short-channel effects is maintained and a high level of transistor current is provided in the strong inversion mode. Based on this architecture, a TCAD model of the NAND gate has been developed, the design of which contains two independent surrounding gates one combined working area. The use of the proposed gate architecture makes it possible to reduce the number of required transistor structures per gate by three times. This leads to a decrease in the switched capacity and power dissipation. From the simulation results, the gate geometric parameters with a working area length of 25 nm and a diameter of 8.5 nm, which can function at control voltages of 0.5 V in the frequency range up to 20 GHz with high gain, are determined. The switching time delay is 0.81 ps. The TCAD model of a half-adder is developed in the basis 2NAND. According to the simulation results, the efficiency of the prototype, which performs binary code addition operations with a delay of 4.2 ps at a supply voltage of 0.5 V and a frequency of 20 GHz, is shown. The obtained results create a theoretical basis for the synthesis of low-voltage complex functional blocks with high performance and minimal occupied area, which meets modern requirements for digital applications.

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

The FinFET architecture has attracted growing attention over the last two decades since its invention, owing to the good control of the gate electrode over the conductive channel leading to a high immunity from short-channel effects (SCEs). In order to contribute to the advancement of this rapidly expanding technology, a 3D 14-nm SOI n-FinFET is performed and calibrated to the experimental data from IBM by using Silvaco TCAD tools. The calibrated TCAD model is then investigated to analyze the impact of changing the fin width, fin height, gate dielectric material, and gate length on the DC and RF parameters. The achieved results allow gaining a better understanding and a deeper insight into the effects of varying the physical dimensions and materials on the device performance, thereby enabling the fabrication of a device tailored to the given constraints and requirements. After analyzing the optimal values from different changes, a new device configuration is proposed, which shows a good improvement in electrical characteristics.

A Rigorous Analysis of Self-Heating Effects in Nanoscale Dielectric Pocket Double-Gate-All-Around (DP-DGAA) MOSFETs

Dielectric Pocket Double-Gate-All-Around (DP-DGAA) MOSFETs are one of the preferred choices for ULSI applications because of significantly low off-current, reduced power dissipation, and high immunity to short channel effect. However, DP-DGAA MOSFETs suffer from self-heating owing to the unavailability of proper heat take-out paths. In this paper, the electrothermal (ET) simulations have been performed with hydrodynamic and thermodynamic transport models to analyze the self-heating effects (SHEs) in DP-DGAA MOSFETs. The electrothermal characteristics against various device parameters such as spacer length, device thickness, thermal contact resistance, and drain voltage have been investigated. The effect of SHE on the drive current has also been evaluated. Further, the impact of thermal contact resistance and ambient temperature variations of the device on SHE and thermal noise have been analyzed using Sentaurus TCAD simulator.

Investigation of short-channel design on performance optimization effect of Hall thruster with large height-radius ratio

In this study, the neutral gas distribution and steady-state discharge under different discharge channel lengths were studied via numerical simulations. The results show that the channel with a length of 22 mm has the advantage of comprehensive discharge performance. At this time, the magnetic field intensity at the anode surface is 10% of the peak magnetic field intensity. Further analysis shows that the high-gas-density zone moves outward due to the shortening of the channel length, which optimizes the matching between the gas flow field and the magnetic field, and thus increases the ionization rate. The outward movement of the main ionization zone also reduces the ion loss on the wall surface. Thus, the propellant utilization efficiency can reach a maximum of 96.8%. Moreover, the plasma potential in the main ionization zone will decrease with the shortening of the channel. The excessively short channel will greatly reduce the voltage utilization efficiency. The thrust is reduced to a minimum of 46.1 mN. Meanwhile, because the anode surface is excessively close to the main ionization zone, the discharge reliability is also difficult to guarantee. It was proved that the performance of Hall thrusters can be optimized by shortening the discharge channel appropriately, and the specific design scheme of short channel of HEP-1350PM was defined, which serves as a reference for the optimization design of Hall thruster with large height-radius ratio. The short-channel design also helps to reduce the thruster axial dimension, further consolidating the advantages of lightweight and large thrust-to-weight ratio of the Hall thruster with large height-radius ratio.