2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
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9781728106557

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Journey to 5G

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8742033 ◽

2019 ◽

Author(s):

Li Fung Chang

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Embedded Memory: The Future of Emerging Memories

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8741732 ◽

2019 ◽

Author(s):

Feng-Min Lee

Keyword(s):

Embedded Memory ◽

The Future

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A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8741773 ◽

2019 ◽

Author(s):

Chao-Jun Shang ◽

Cheng-Hung Wu ◽

Kuen-Jong Lee ◽

Yu-Hsiang Chen

Keyword(s):

Test Generation ◽

Fault Model ◽

Small Delay Defects ◽

Small Delay ◽

Delay Defects

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An Analog Front-End Circuit for CO2 Sensor Readout in 0.18-µm CMOS Process

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8741403 ◽

2019 ◽

Author(s):

Deng-Kai Lin ◽

Chih-Chan Tu ◽

Shih-Kai Kuo ◽

Tsung-Hsien Lin

Keyword(s):

Cmos Process ◽

Co2 Sensor ◽

Front End ◽

Analog Front End

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Supervised-Learning Congestion Predictor For Routability-Driven Global Routing

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8742060 ◽

2019 ◽

Cited By ~ 1

Author(s):

Zhonghua Zhou ◽

Sunmeet Chahal ◽

Tsung-Yi Ho ◽

Andre Ivanov

Keyword(s):

Supervised Learning ◽

Global Routing

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TSRI Silicon Photonics Design Platform: Standardization and Collaboration

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8741803 ◽

2019 ◽

Author(s):

Ming-Wei Lin

Keyword(s):

Silicon Photonics

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10-Bit SAR ADC With Novel Pseudo-Random Capacitor Switching Scheme

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8741534 ◽

2019 ◽

Author(s):

Pai-Hsiang Hsu ◽

Yueh-Ru Lee ◽

Chung-Chih Hung

Keyword(s):

Sar Adc ◽

Switching Scheme ◽

Capacitor Switching

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Flexible Circuits and Systems for Smart Biomedical Applications

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8742032 ◽

2019 ◽

Author(s):

Yongpan Liu

Keyword(s):

Biomedical Applications

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Efficient Write Scheme for Algorithm-Based Multi-Ported Memory

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8741927 ◽

2019 ◽

Cited By ~ 1

Author(s):

Bo-Ya Chen ◽

Bo-En Chen ◽

Bo-Cheng Lai

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A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with Averaging Correlated Level Shifting Technique

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vlsi-dat.2019.8741986 ◽

2019 ◽

Author(s):

Jia-Ching Wang ◽

Tsung-Chih Hung ◽

Tai-Haur Kuo

Keyword(s):

Pipelined Adc ◽

Correlated Level Shifting

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2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Journey to 5G

Embedded Memory: The Future of Emerging Memories

A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model

An Analog Front-End Circuit for CO2 Sensor Readout in 0.18-µm CMOS Process

Supervised-Learning Congestion Predictor For Routability-Driven Global Routing

TSRI Silicon Photonics Design Platform: Standardization and Collaboration

10-Bit SAR ADC With Novel Pseudo-Random Capacitor Switching Scheme

Flexible Circuits and Systems for Smart Biomedical Applications

Efficient Write Scheme for Algorithm-Based Multi-Ported Memory

A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with Averaging Correlated Level Shifting Technique

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
Latest Publications