2007 IEEE Northeast Workshop on Circuits and Systems
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

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(FIVE YEARS 0)

Published By IEEE

9781424411634, 9781424411641

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A new encoder implementation for low-density parity-check convolutional codes

2007 IEEE Northeast Workshop on Circuits and Systems ◽

10.1109/newcas.2007.4487987 ◽

2007 ◽

Cited By ~ 2

Author(s):

Zhengang Chen ◽

Ramkrishna Swamy ◽

Stephen Bates

Keyword(s):

Convolutional Codes ◽

Low Density ◽

Parity Check ◽

Low Density Parity Check

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A new subthreshold leakage model for NMOS transistor stacks

2007 IEEE Northeast Workshop on Circuits and Systems ◽

10.1109/newcas.2007.4487994 ◽

2007 ◽

Cited By ~ 3

Author(s):

Hussam Al-Hertani ◽

Dhamin Al-Khalili ◽

Come Rozon

Keyword(s):

Nmos Transistor ◽

Leakage Model ◽

Subthreshold Leakage

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A single-chip ring-based multiprocessor with region-level filtering of coherence traffic

2007 IEEE Northeast Workshop on Circuits and Systems ◽

10.1109/newcas.2007.4488016 ◽

2007 ◽

Cited By ~ 2

Author(s):

Edmond Cote ◽

Naraig Manjikian

Keyword(s):

Single Chip

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System-level design aspects of a DAC Calibration technique for bandpass delta-sigma modulators

2007 IEEE Northeast Workshop on Circuits and Systems ◽

10.1109/newcas.2007.4488027 ◽

2007 ◽

Author(s):

Ghyslain Gagnon ◽

Leonard MacEachern

Keyword(s):

System Level ◽

System Level Design ◽

Calibration Technique ◽

Delta Sigma ◽

Level Design

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Digital filtering of toroidal sensor-array signals using 3D IIR frequency-planar filters

2007 IEEE Northeast Workshop on Circuits and Systems ◽

10.1109/newcas.2007.4487975 ◽

2007 ◽

Cited By ~ 1

Author(s):

H. L. P. Arjuna Madanayake ◽

Leonard T. Bruton

Keyword(s):

Sensor Array ◽

Digital Filtering

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Optimal spacing for a polar look-up table predistorter

2007 IEEE Northeast Workshop on Circuits and Systems ◽

10.1109/newcas.2007.4487958 ◽

2007 ◽

Cited By ~ 3

Author(s):

Seydou N. Ba ◽

Khurram Waheed ◽

G. Tong Zhou

Keyword(s):

Look Up Table ◽

Optimal Spacing

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On the performance of double-gate MOSFET circuit applications

2007 IEEE Northeast Workshop on Circuits and Systems ◽

10.1109/newcas.2007.4487973 ◽

2007 ◽

Cited By ~ 2

Author(s):

Ilham Hassoune ◽

Ian O'Connor ◽

David Navarro

Keyword(s):

Double Gate ◽

Double Gate Mosfet

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A 1-V fully differential sample-and-hold circuit using hybrid cascode compensated DTMOS-based folded OTA

2007 IEEE Northeast Workshop on Circuits and Systems ◽

10.1109/newcas.2007.4487952 ◽

2007 ◽

Cited By ~ 1

Author(s):

Christian J. B. Fayomi ◽

Herve F. Achigui ◽

Gilson I. Wirth ◽

Tadeusz Kwasniewski

Keyword(s):

Fully Differential ◽

Sample And Hold

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Timing-constrained redundant via insertion for yield optimization

2007 IEEE Northeast Workshop on Circuits and Systems ◽

10.1109/newcas.2007.4488005 ◽

2007 ◽

Cited By ~ 1

Author(s):

Jin-Tai Yan ◽

Bo-Yi Chiang ◽

Zhi-Wei Chen

Keyword(s):

Yield Optimization

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Design techniques for high speed current steering DACs

2007 IEEE Northeast Workshop on Circuits and Systems ◽

10.1109/newcas.2007.4488028 ◽

2007 ◽

Cited By ~ 2

Author(s):

Iliasse Benamrane ◽

Yvon Savaria

Keyword(s):

High Speed ◽

Current Steering ◽

Design Techniques

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2007 IEEE Northeast Workshop on Circuits and SystemsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A new encoder implementation for low-density parity-check convolutional codes

A new subthreshold leakage model for NMOS transistor stacks

A single-chip ring-based multiprocessor with region-level filtering of coherence traffic

System-level design aspects of a DAC Calibration technique for bandpass delta-sigma modulators

Digital filtering of toroidal sensor-array signals using 3D IIR frequency-planar filters

Optimal spacing for a polar look-up table predistorter

On the performance of double-gate MOSFET circuit applications

A 1-V fully differential sample-and-hold circuit using hybrid cascode compensated DTMOS-based folded OTA

Timing-constrained redundant via insertion for yield optimization

Design techniques for high speed current steering DACs

2007 IEEE Northeast Workshop on Circuits and Systems
Latest Publications