Double-Quantum-Well AlGaN/GaN Field Effect Transistors with Top and Back Gates: Electrical and Noise Characteristics

AlGaN/GaN fin-shaped and large-area grating gate transistors with two layers of two-dimensional electron gas and a back gate were fabricated and studied experimentally. The back gate allowed reducing the subthreshold leakage current, improving the subthreshold slope and adjusting the threshold voltage. At a certain back gate voltage, transistors operated as normally-off devices. Grating gate transistors with a high gate area demonstrated little subthreshold leakage current, which could be further reduced by the back gate. The low frequency noise measurements indicated identical noise properties and the same trap density responsible for noise when the transistors were controlled by either top or back gates. This result was explained by the tunneling of electrons to the traps in AlGaN as the main noise mechanism. The trap density extracted from the noise measurements was similar or less than that reported in the majority of publications on regular AlGaN/GaN transistors.

Design of CNTFET Based Domino Wide OR Gates Using Dual Chirality for Reducing Subthreshold Leakage Current

The leakage current is prime concern in the modern portable battery operated device. However, various techniques are presented and performance is evaluated using MOSFET and FinFET devices. To further reduce leakage current for improved battery backup in portable devices, new devicesnamely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. Subthreshold leakage power saving in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25°C) & low input ranges from 90.36- 95.96% and from 91.97-97.3%; for low temperature & high input ranges from 90.66-95.23% and from 92.85-96.39%; for high temperature (110°C) & low input ranges from 89.24- 99.73% and from 27.5-99.83%; for high temperature & high input ranges from 89.65-97.86% and from 91.85-99.76% when compared with single chiral standard and LECTOR based domino circuits respectively.

Modelling and Simulation of Tri-layered (s-Si/s-SiGe/s-Si) Channel Double Gate Nano FET

The down scaling of Meatal Oxide Semiconductor Field Effect transistor (MOSFET) devices nevertheless the most important and effective way for accomplishing high performance with low power adopted the miniaturization trend of channel length from the past, which is very aggressive. The double gate NanoFET with the incorporation of the strain Silicon technology is developed here on 45nm gate length comprises of tri-layered (s-Si/s-SiGe/s-Si) channel region with varied thicknesses. The induction of strain increases mobility of charge carriers. Two gates are deployed in bottom and up side of strained channel provides better control over the depletion region developed by applying same gate bias voltage. This newly developed double gate NanoFET on 45nm channel length provides 63% reduced subthreshold leakage current, and maximum electron drift velocity in strained channel.