Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)
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Test synthesis for DC test and maximal diagnosis of switched-capacitor circuits

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.600284 ◽

2002 ◽

Cited By ~ 11

Author(s):

C. Dufaza ◽

H. IHS

Keyword(s):

Switched Capacitor ◽

Switched Capacitor Circuits ◽

Test Synthesis

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Using ATPG for clock rules checking in complex scan designs

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.599463 ◽

2002 ◽

Cited By ~ 6

Author(s):

P. Wohl ◽

J. Waicukauski

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BIST TPGs for faults in board level interconnect via boundary scan

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.600311 ◽

2002 ◽

Cited By ~ 16

Author(s):

Chen-Haun Chiang ◽

S.K. Gupta

Keyword(s):

Boundary Scan ◽

Board Level

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Automated test pattern generation for analog integrated circuits

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.600291 ◽

2002 ◽

Cited By ~ 16

Author(s):

W. Verhaegen ◽

G. Van der Plas ◽

G. Gielen

Keyword(s):

Integrated Circuits ◽

Test Pattern ◽

Analog Integrated Circuits ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automated Test

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Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.600285 ◽

2002 ◽

Cited By ~ 12

Author(s):

P.N. Variyam ◽

A. Chatterjeee ◽

N. Nagi

Keyword(s):

Analog Circuits ◽

Low Cost ◽

Pulse Response

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A linear code-preserving signature analyzer COPMISR

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.600303 ◽

2002 ◽

Cited By ~ 1

Author(s):

A. Hlawiczka ◽

M. Gossel ◽

E.S. Sogormonyan

Keyword(s):

Linear Code ◽

Signature Analyzer

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Implicit test pattern generation constrained to cellular automata embedding

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.599441 ◽

2002 ◽

Cited By ~ 5

Author(s):

F. Fummi ◽

D. Sciuto

Keyword(s):

Cellular Automata ◽

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Implicit Test

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An on-line testable UART implemented using IFIS

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.600301 ◽

2002 ◽

Cited By ~ 1

Author(s):

J. Yeandel ◽

D. Thulborn ◽

S. Jones

Keyword(s):

On Line

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Fault coverage of a long random test sequence estimated from a short simulation

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.600315 ◽

2002 ◽

Cited By ~ 1

Author(s):

V. Prepin ◽

R. David

Keyword(s):

Fault Coverage ◽

Test Sequence ◽

Random Test

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A high-level synthesis approach to design of fault-tolerant systems

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125) ◽

10.1109/vtest.1997.600305 ◽

2002 ◽

Cited By ~ 6

Author(s):

G. Buonanno ◽

M. Pugassi ◽

M.G. Sami

Keyword(s):

Fault Tolerant ◽

High Level Synthesis ◽

Fault Tolerant Systems ◽

High Level ◽

Synthesis Approach

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Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Test synthesis for DC test and maximal diagnosis of switched-capacitor circuits

Using ATPG for clock rules checking in complex scan designs

BIST TPGs for faults in board level interconnect via boundary scan

Automated test pattern generation for analog integrated circuits

Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling

A linear code-preserving signature analyzer COPMISR

Implicit test pattern generation constrained to cellular automata embedding

An on-line testable UART implemented using IFIS

Fault coverage of a long random test sequence estimated from a short simulation

A high-level synthesis approach to design of fault-tolerant systems

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)
Latest Publications