Records of the IEEE International Workshop on Memory Technology, Design and Testing
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TOTAL DOCUMENTS

20

(FIVE YEARS 0)

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6

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Published By IEEE

0769506895

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Failure mechanisms in semiconductor memory circuits

Records of the IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2000.868609 ◽

2002 ◽

Author(s):

R. Haythornthwaite

Keyword(s):

Failure Mechanisms ◽

Semiconductor Memory ◽

Memory Circuits

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A low voltage embedded single port SRAM generator in a 0.18 μm standard CMOS process

Records of the IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2000.868623 ◽

2002 ◽

Author(s):

C. Frey ◽

F. Genevaux ◽

C. Issartel ◽

D. Turgis ◽

J.P. Schoellkopf

Keyword(s):

Low Voltage ◽

Single Port ◽

Cmos Process ◽

Standard Cmos Process

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Fast voltage regulator for multilevel flash memories

Records of the IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2000.868613 ◽

2002 ◽

Author(s):

O. Khouri ◽

R. Micheloni ◽

S. Gregori ◽

G. Torelli

Keyword(s):

Voltage Regulator ◽

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Windowed MRAM sensing scheme

Records of the IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2000.868615 ◽

2002 ◽

Author(s):

R. Zhang ◽

W.C. Black ◽

M.M. Hassoun

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66 MHz 2.3 M ternary dynamic content addressable memory

Records of the IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2000.868622 ◽

2002 ◽

Author(s):

V. Lines ◽

A. Ahmed ◽

P. Ma ◽

S. Ma ◽

R. McKenzie ◽

...

Keyword(s):

Content Addressable Memory ◽

Dynamic Content

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Design techniques for embedded EEPROM memories in portable ASIC and ASSP solutions

Records of the IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2000.868614 ◽

2002 ◽

Author(s):

J.M. Daga ◽

C. Papaix ◽

M. Merandat ◽

S. Ricard ◽

G. Medulla ◽

...

Keyword(s):

Design Techniques

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Defect analysis and realistic fault model extensions for static random access memories

Records of the IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2000.868625 ◽

2002 ◽

Author(s):

K. Zarrineh ◽

A.P. Deo ◽

R.D. Adams

Keyword(s):

Random Access ◽

Fault Model ◽

Defect Analysis ◽

Static Random Access Memories

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Hierarchical sector biasing organization for flash memories

Records of the IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2000.868612 ◽

2002 ◽

Author(s):

R. Micheloni ◽

M. Zammattio ◽

G. Campardo ◽

O. Khouri ◽

G. Torelli

Keyword(s):

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Yield analysis methodology for low defectivity wafer fabs

Records of the IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2000.868617 ◽

2002 ◽

Author(s):

K. Rajkanan

Keyword(s):

Yield Analysis ◽

Analysis Methodology

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Diagnostic testing of embedded memories based on output tracing

Records of the IEEE International Workshop on Memory Technology, Design and Testing ◽

10.1109/mtdt.2000.868624 ◽

2002 ◽

Author(s):

D. Niggemeyer ◽

M. Redeker ◽

E.M. Rudnick

Keyword(s):

Diagnostic Testing ◽

Embedded Memories

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