2020 IEEE International Solid- State Circuits Conference - (ISSCC)
Latest Publications

TOTAL DOCUMENTS

272

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781728132051

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9062965 ◽

2020 ◽

Cited By ~ 1

Author(s):

Kasho Yamamoto ◽

Kota Ando ◽

Normann Mertig ◽

Takashi Takemoto ◽

Masanao Yamaoka ◽

...

Keyword(s):

Combinatorial Optimization ◽

Spin Interactions

Short Course: Circuit Design in Advanced CMOS Technologies — Considerations and Solutions

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063028 ◽

2020 ◽

Keyword(s):

Circuit Design ◽

Short Course

Session 8 Overview: Highlighted Chip Releases: Industry Showcase Committee

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063098 ◽

2020 ◽

Session 19 Overview: CRYO-CMOS for Quantum Technologies: Technology Directions Subcommittee

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063084 ◽

2020 ◽

Foreword

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063166 ◽

2020 ◽

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9062908 ◽

2020 ◽

Cited By ~ 1

Author(s):

Masanori Hashimoto ◽

Xu Bai ◽

Naoki Banno ◽

Munehiro Tada ◽

Toshitsugu Sakamoto ◽

...

Keyword(s):

Cmos Implementation

17.4 A 18.6-to-40.1GHz 201.7dBc/Hz FoMT Multi-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063100 ◽

2020 ◽

Author(s):

Yiyang Shu ◽

Huizhen Jenny Qian ◽

Xun Luo

10.8 A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063106 ◽

2020 ◽

Cited By ~ 2

Author(s):

Erfan Ghaderi ◽

Chase Puglisi ◽

Shrestha Bansal ◽

Subhanshu Gupta

Keyword(s):

Digital Converter ◽

Time To Digital Converter ◽

Signal Processor

32.3 Electromagnetic Mechanical Energy-Harvester IC with No Off-Chip Component and One Switching Period MPPT Achieving up to 95.9% End-to-End Efficiency and 460% Energy-Extraction Gain

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063023 ◽

2020 ◽

Author(s):

Anthony Quelen ◽

Gael Pillonnet ◽

Pierre Gasnier ◽

Francois Rummens ◽

Sebastien Boisseau

Keyword(s):

Energy Harvester ◽

Mechanical Energy ◽

Energy Extraction ◽

End To End

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063158 ◽

2020 ◽

Author(s):

Mark A. Anders ◽

Himanshu Kaul ◽

Seongjong Kim ◽

Gregory K. Chen ◽

Raghavan Kumar ◽

...

Keyword(s):

High Performance ◽

Current Mode ◽

Transient Current ◽

Operating Range ◽

Voltage Frequency ◽

Global Interconnect ◽

Interconnect Circuits

2020 IEEE International Solid- State Circuits Conference - (ISSCC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions

Short Course: Circuit Design in Advanced CMOS Technologies — Considerations and Solutions

Session 8 Overview: Highlighted Chip Releases: Industry Showcase Committee

Session 19 Overview: CRYO-CMOS for Quantum Technologies: Technology Directions Subcommittee

Foreword

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications

17.4 A 18.6-to-40.1GHz 201.7dBc/Hz FoMT Multi-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting

10.8 A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS

32.3 Electromagnetic Mechanical Energy-Harvester IC with No Off-Chip Component and One Switching Period MPPT Achieving up to 95.9% End-to-End Efficiency and 460% Energy-Extraction Gain

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

2020 IEEE International Solid- State Circuits Conference - (ISSCC)
Latest Publications