VLSI Signal Processing, VIII
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60

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8

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Published By IEEE

0780326121

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

NORMALISED GIVENS ROTATIONS FOR RECURSIVE LEAST SQUARES PROCESSING

VLSI Signal Processing, VIII ◽

10.1109/vlsisp.1995.527502 ◽

2005 ◽

Cited By ~ 1

Author(s):

J.G. McWhirter ◽

J. Kadlec ◽

R.L. Walke

Keyword(s):

Least Squares ◽

Recursive Least Squares ◽

Givens Rotations

Redundant complex number arithmetic for high-speed signal processing

VLSI Signal Processing, VIII ◽

10.1109/vlsisp.1995.527523 ◽

2002 ◽

Cited By ~ 18

Author(s):

T. Aoki ◽

Y. Ohki ◽

T. Higuchi

Keyword(s):

Signal Processing ◽

Complex Number ◽

High Speed

An algorithm adapted autonomous controlling concept for a parallel single-chip digital signal processor

VLSI Signal Processing, VIII ◽

10.1109/vlsisp.1995.527475 ◽

2002 ◽

Cited By ~ 1

Author(s):

J. Kneip ◽

J.P. Wittenburg ◽

M. Berekovic ◽

K. Ronner ◽

P. Pirsch

Keyword(s):

Digital Signal Processor ◽

Digital Signal ◽

Single Chip ◽

Signal Processor

A method of data path allocation by pattern matching on the data flow graph

VLSI Signal Processing, VIII ◽

10.1109/vlsisp.1995.527497 ◽

2002 ◽

Cited By ~ 1

Author(s):

Y. Hirakawa ◽

M. Yoshida ◽

K. Harashima ◽

K. Fukunaga

Keyword(s):

Pattern Matching ◽

Data Flow ◽

Data Path ◽

Data Flow Graph ◽

Flow Graph

An LSI architecture for block-matching motion estimation algorithm considering chrominance signal

VLSI Signal Processing, VIII ◽

10.1109/vlsisp.1995.527513 ◽

2002 ◽

Cited By ~ 1

Author(s):

E. Iwata ◽

T. Yamazaki

Keyword(s):

Motion Estimation ◽

Estimation Algorithm ◽

Block Matching ◽

Motion Estimation Algorithm

A systolic array for sliding window constrained RLS

VLSI Signal Processing, VIII ◽

10.1109/vlsisp.1995.527504 ◽

2002 ◽

Author(s):

H. Sakai ◽

M. Kuroda

Keyword(s):

Systolic Array ◽

Sliding Window

A parametric DCT macro cell generator with a simulation model and an accuracy report

VLSI Signal Processing, VIII ◽

10.1109/vlsisp.1995.527515 ◽

2002 ◽

Author(s):

M. Ohki ◽

T. Nagai ◽

M. Aikawa ◽

K. Seno

Keyword(s):

Simulation Model ◽

Macro Cell

A unified cellular array for multiplication, division and square root

VLSI Signal Processing, VIII ◽

10.1109/vlsisp.1995.527524 ◽

2002 ◽

Author(s):

San-Gee Chen ◽

Chieh-Chih Li

Keyword(s):

Square Root ◽

Cellular Array

A scalable systolic array architecture for 2D discrete wavelet transforms

VLSI Signal Processing, VIII ◽

10.1109/vlsisp.1995.527501 ◽

2002 ◽

Cited By ~ 19

Author(s):

J. Chen ◽

M.A. Bayoumi

Keyword(s):

Systolic Array ◽

Wavelet Transforms ◽

Discrete Wavelet ◽

Discrete Wavelet Transforms ◽

Array Architecture

A single-chip MPEG1 audio/video decoder using macrocore and cell-base implementation

VLSI Signal Processing, VIII ◽

10.1109/vlsisp.1995.527514 ◽

2002 ◽

Cited By ~ 4

Author(s):

Y. Katayama ◽

I. Tamitani ◽

A. Taniguchi ◽

Y. Ooi

Keyword(s):

Single Chip ◽

Video Decoder ◽

Audio Video ◽

Cell Base