Communications in Computer and Information Science - Computer Engineering and Technology
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Published By Springer Berlin Heidelberg

9783642358975, 9783642358982

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HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip

Communications in Computer and Information Science - Computer Engineering and Technology ◽

10.1007/978-3-642-35898-2_18 ◽

2013 ◽

pp. 155-162

Author(s):

Liguo Zhang ◽

Huimin Du ◽

Jianyuan Liu

Keyword(s):

Network On Chip ◽

On Chip

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ADL and High Performance Processor Design

Communications in Computer and Information Science - Computer Engineering and Technology ◽

10.1007/978-3-642-35898-2_8 ◽

2013 ◽

pp. 67-74

Author(s):

Liu Yang ◽

Xiaoqiang Ni ◽

Yusong Tan ◽

Hengzhu Liu

Keyword(s):

High Performance ◽

Processor Design

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MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processor

Communications in Computer and Information Science - Computer Engineering and Technology ◽

10.1007/978-3-642-35898-2_3 ◽

2013 ◽

pp. 16-26 ◽

Cited By ~ 2

Author(s):

Xiaobo Yan ◽

Rangyu Deng ◽

Caixia Sun ◽

Qiang Dou

Keyword(s):

Multi Level

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On Stepsize of Fast Subspace Tracking Methods

Communications in Computer and Information Science - Computer Engineering and Technology ◽

10.1007/978-3-642-35898-2_27 ◽

2013 ◽

pp. 253-261

Author(s):

Zhu Cheng ◽

Zhan Wang ◽

Haitao Liu ◽

Majid Ahmadi

Keyword(s):

Subspace Tracking

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A Novel Graph Model for Loop Mapping on Coarse-Grained Reconfigurable Architectures

Communications in Computer and Information Science - Computer Engineering and Technology ◽

10.1007/978-3-642-35898-2_25 ◽

2013 ◽

pp. 231-241

Author(s):

Ziyu Yang ◽

Ming Yan ◽

Dawei Wang ◽

Sikun Li

Keyword(s):

Graph Model ◽

Coarse Grained ◽

Reconfigurable Architectures

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Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Method

Communications in Computer and Information Science - Computer Engineering and Technology ◽

10.1007/978-3-642-35898-2_2 ◽

2013 ◽

pp. 8-15

Author(s):

Shengfei Wu ◽

Jiang Jiang ◽

Yuzhuo Fu

Keyword(s):

Hardware Architecture ◽

Random Numbers ◽

Long Period

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A Method of Balancing the Global Multi-mode Clock Network in Ultra-large Scale CPU

Communications in Computer and Information Science - Computer Engineering and Technology ◽

10.1007/978-3-642-35898-2_1 ◽

2013 ◽

pp. 1-7

Author(s):

Zhuo Ma ◽

Zhenyu Zhao ◽

Yang Guo ◽

Lunguo Xie ◽

Jinshan Yu

Keyword(s):

Large Scale ◽

Clock Network ◽

Multi Mode

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Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip

Communications in Computer and Information Science - Computer Engineering and Technology ◽

10.1007/978-3-642-35898-2_17 ◽

2013 ◽

pp. 148-154

Author(s):

Peng Wu ◽

Yuzhuo Fu ◽

Jiang Jiang

Keyword(s):

Network On Chip ◽

Virtual Channel ◽

Design And Implementation ◽

On Chip

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The Design and Realization of Campus Information Release Platform Based on Android Framework

Communications in Computer and Information Science - Computer Engineering and Technology ◽

10.1007/978-3-642-35898-2_14 ◽

2013 ◽

pp. 121-128

Author(s):

Jie Wang ◽

Xue Yu ◽

Yu Zeng ◽

Dongri Yang

Keyword(s):

Information Release

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A Combined Hardware/Software Measurement for ARM Program Execution Time

Communications in Computer and Information Science - Computer Engineering and Technology ◽

10.1007/978-3-642-35898-2_21 ◽

2013 ◽

pp. 185-201

Author(s):

Liangliang Kong ◽

Jianhui Jiang

Keyword(s):

Execution Time ◽

Program Execution ◽

Software Measurement

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Communications in Computer and Information Science - Computer Engineering and TechnologyLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer Berlin Heidelberg

HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip

ADL and High Performance Processor Design

MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processor

On Stepsize of Fast Subspace Tracking Methods

A Novel Graph Model for Loop Mapping on Coarse-Grained Reconfigurable Architectures

Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Method

A Method of Balancing the Global Multi-mode Clock Network in Ultra-large Scale CPU

Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip

The Design and Realization of Campus Information Release Platform Based on Android Framework

A Combined Hardware/Software Measurement for ARM Program Execution Time

Communications in Computer and Information Science - Computer Engineering and Technology
Latest Publications