2020 24th International Symposium on VLSI Design and Test (VDAT)
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 58)

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(FIVE YEARS 0)

Published By IEEE

9781728193694

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing

2020 24th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/vdat50263.2020.9190402 ◽

2020 ◽

Author(s):

Smrutilekha Samanta ◽

Santanu Sarkar

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Design of Transceiver at 865–867 MHz Band using UMC 180 nm CMOS Technology

2020 24th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/vdat50263.2020.9190468 ◽

2020 ◽

Author(s):

Jai Shankar Kumar ◽

Babli Kumari ◽

Prashant Kumar ◽

Ankita Verma ◽

Pritesh Kumar Yadav ◽

...

Keyword(s):

Cmos Technology

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Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate

2020 24th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/vdat50263.2020.9190409 ◽

2020 ◽

Author(s):

Subhadip Poria ◽

Shelly Garg ◽

Sneh Saurabh

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Field Plate ◽

Effect Transistor ◽

Ambipolar Current ◽

Tunnel Field Effect Transistor

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Artificial Neural Network Model for Design Optimization of 2-stage Op-amp

2020 24th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/vdat50263.2020.9190315 ◽

2020 ◽

Author(s):

Harsha M.V. ◽

B. P. Harish

Keyword(s):

Neural Network ◽

Artificial Neural Network ◽

Design Optimization ◽

Network Model ◽

Neural Network Model ◽

Artificial Neural Network Model ◽

Op Amp ◽

Artificial Neural

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Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis

2020 24th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/vdat50263.2020.9190571 ◽

2020 ◽

Author(s):

Sisir Kumar Jena ◽

Santosh Biswas ◽

Jatindra Kumar Deka

Keyword(s):

Fault Analysis ◽

Vlsi Circuits ◽

Digital Vlsi

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Automatic Inverse Operation Detection and its Impact in High-level Synthesis

2020 24th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/vdat50263.2020.9190276 ◽

2020 ◽

Author(s):

Pankaj Kumar Kalita ◽

Ramanuj Chouksey ◽

Chandan Karfa

Keyword(s):

High Level Synthesis ◽

High Level ◽

Inverse Operation

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Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm

2020 24th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/vdat50263.2020.9190560 ◽

2020 ◽

Author(s):

B B Shabarinath ◽

P. Muralidhar

Keyword(s):

Gradient Descent ◽

Design Paradigm

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3D-NoCNN: NoC based Clustered Architecture for Neural Networks

2020 24th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/vdat50263.2020.9190590 ◽

2020 ◽

Author(s):

Aneek Jash ◽

Ayut Ghosh ◽

Naif Noyel ◽

Ramapati Patra ◽

Hemanta Kumar Mondal

Keyword(s):

Neural Networks

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A Highly Stable and Robust 7T SRAM Cell using Memristor

2020 24th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/vdat50263.2020.9190585 ◽

2020 ◽

Author(s):

Sahan Panguluru ◽

Jai Gopal Pandey

Keyword(s):

Sram Cell

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Design and Analysis of Secure One-way Functions for the Protection of Symmetric Key Cryptosystems

2020 24th International Symposium on VLSI Design and Test (VDAT) ◽

10.1109/vdat50263.2020.9190432 ◽

2020 ◽

Author(s):

Surbhi Chhabra ◽

Vishakha Dhanwani ◽

Vikas Kumar Dhaka ◽

Kusum Lata

Keyword(s):

Symmetric Key

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2020 24th International Symposium on VLSI Design and Test (VDAT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing

Design of Transceiver at 865–867 MHz Band using UMC 180 nm CMOS Technology

Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate

Artificial Neural Network Model for Design Optimization of 2-stage Op-amp

Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis

Automatic Inverse Operation Detection and its Impact in High-level Synthesis

Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm

3D-NoCNN: NoC based Clustered Architecture for Neural Networks

A Highly Stable and Robust 7T SRAM Cell using Memristor

Design and Analysis of Secure One-way Functions for the Protection of Symmetric Key Cryptosystems

2020 24th International Symposium on VLSI Design and Test (VDAT)
Latest Publications