Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05
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Prediction of delay time for future LSI using on-chip transmission line interconnects

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05 ◽

10.1145/1053355.1053359 ◽

2005 ◽

Cited By ~ 2

Author(s):

Takumi Uezono ◽

Junpei Inoue ◽

Takanori Kyogoku ◽

Kenichi Okada ◽

Kazuya Masu

Keyword(s):

Transmission Line ◽

Delay Time ◽

On Chip

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Congestion prediction in early stages

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05 ◽

10.1145/1053355.1053376 ◽

2005 ◽

Cited By ~ 11

Author(s):

Chiu-wing Sham ◽

Evangeline F. Y. Young

Keyword(s):

Early Stages ◽

Congestion Prediction

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Package level interconnect options

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05 ◽

10.1145/1053355.1053361 ◽

2005 ◽

Cited By ~ 7

Author(s):

J. Balachandran ◽

S. Brebels ◽

G. Carchon ◽

T. Webers ◽

W. De Raedt ◽

...

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High-performance ULSI

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05 ◽

10.1145/1053355.1053357 ◽

2005 ◽

Cited By ~ 1

Author(s):

Ron Ho

Keyword(s):

High Performance

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Is probabilistic congestion estimation worthwhile?

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05 ◽

10.1145/1053355.1053377 ◽

2005 ◽

Cited By ~ 25

Author(s):

Jurjen Westra ◽

Patrick Groeneveld

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Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05 ◽

10.1145/1053355.1053366 ◽

2005 ◽

Cited By ~ 5

Author(s):

M. Y. Lanzerotti ◽

G. Fiorenza ◽

R. A. Rand

Keyword(s):

Large Scale ◽

Integrated Control ◽

Control Logic

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The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05 ◽

10.1145/1053355.1053372 ◽

2005 ◽

Cited By ~ 1

Author(s):

Viet H. Nguyen ◽

Phillip Christie

Keyword(s):

Integrated Circuits ◽

Three Dimensional ◽

The Impact

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Dealing with the spatio-temporal interactions among transient power, supply noise and timing

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05 ◽

10.1145/1053355.1053369 ◽

2005 ◽

Author(s):

David Hathaway

Keyword(s):

Power Supply ◽

Power Supply Noise ◽

Supply Noise ◽

Spatio Temporal ◽

Temporal Interactions

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Multilevel full-chip routing with testability and yield enhancement

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05 ◽

10.1145/1053355.1053362 ◽

2005 ◽

Cited By ~ 2

Author(s):

Katherine Shu-Min Li ◽

Chung-Len Lee ◽

Yao-Wen Chang ◽

Chauchin Su ◽

Jwu-E Chen

Keyword(s):

Yield Enhancement

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A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05 ◽

10.1145/1053355.1053371 ◽

2005 ◽

Cited By ~ 3

Author(s):

Young-Su Kwon ◽

Payam Lajevardi ◽

Anantha P. Chandrakasan ◽

Frank Honoré ◽

Donald E. Troxel

Keyword(s):

Prediction Model ◽

Placement And Routing ◽

Resource Prediction

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Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Prediction of delay time for future LSI using on-chip transmission line interconnects

Congestion prediction in early stages

Package level interconnect options

High-performance ULSI

Is probabilistic congestion estimation worthwhile?

Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry

The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits

Dealing with the spatio-temporal interactions among transient power, supply noise and timing

Multilevel full-chip routing with testability and yield enhancement

A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05
Latest Publications