ESD Protection Circuits

2004 ◽

Cited By ~ 6

Author(s):

B. Fankhauser ◽

B. Deutschmann

Keyword(s):

Esd Protection ◽

Protection Circuits

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Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

ETRI Journal ◽

10.4218/etrij.09.1209.0045 ◽

2009 ◽

Vol 31 (6) ◽

pp. 725-731 ◽

Cited By ~ 4

Author(s):

Yong-Seo Koo ◽

Kwangsoo Kim ◽

Shihong Park ◽

Kwidong Kim ◽

Jong-Kee Kwon

Keyword(s):

Leakage Current ◽

Turn On ◽

Low Leakage ◽

Low Leakage Current ◽

Esd Protection ◽

Protection Circuits

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A new I/O signal latchup phenomenon in voltage tolerant ESD protection circuits

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual. ◽

10.1109/relphy.2003.1197725 ◽

2003 ◽

Cited By ~ 7

Author(s):

J. Salcedo-Suner ◽

R. Cline ◽

C. Duvvury ◽

A. Cadena-Hernandez ◽

L. Ting ◽

...

Keyword(s):

Esd Protection ◽

Protection Circuits

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New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. ◽

10.1109/apccas.2004.1413010 ◽

2005 ◽

Author(s):

Ming-Dou Ker ◽

Kuo-Chun Hsu

Keyword(s):

Cmos Technology ◽

Design Concept ◽

Nanoscale Cmos ◽

Esd Protection ◽

Protection Circuits ◽

On Chip

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A physics-based compact model for SCR devices used in ESD protection circuits

2013 IEEE International Reliability Physics Symposium (IRPS) ◽

10.1109/irps.2013.6531947 ◽

2013 ◽

Cited By ~ 10

Author(s):

R. Mertens ◽

E. Rosenbaum

Keyword(s):

Compact Model ◽

Esd Protection ◽

Protection Circuits

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Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6811960 ◽

2013 ◽

Author(s):

Guangyi Lu ◽

Yuan Wang ◽

Jian Cao ◽

Song Jia ◽

Ganggang Zhang ◽

...

Keyword(s):

Gate Voltage ◽

Voltage Bias ◽

Esd Protection ◽

Protection Circuits

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Temperature-dependence of steady-state characteristics of SCR-type ESD protection circuits

Solid-State Electronics ◽

10.1016/s0038-1101(00)00153-2 ◽

2000 ◽

Vol 44 (12) ◽

pp. 2139-2146 ◽

Cited By ~ 8

Author(s):

Sheng-Lyang Jang ◽

Jeng-Kuan Lin

Keyword(s):

Steady State ◽

Temperature Dependence ◽

Esd Protection ◽

Protection Circuits

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Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits

Microelectronics Reliability ◽

10.1016/s0026-2714(01)00034-8 ◽

2001 ◽

Vol 41 (11) ◽

pp. 1781-1787 ◽

Cited By ~ 7

Author(s):

Yu Wang ◽

Patrick Juliano ◽

Sopan Joshi ◽

Elyse Rosenbaum

Keyword(s):

Esd Protection ◽

Protection Circuits

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Analysis and Measurement of Signal Distortion due to ESD Protection Circuits

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2006.881550 ◽

2006 ◽

Vol 41 (10) ◽

pp. 2354-2358 ◽

Cited By ~ 10

Author(s):

J.-H. Chun ◽

B. Murmann

Keyword(s):

Signal Distortion ◽

Esd Protection ◽

Protection Circuits

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Mixed-voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies

Proceedings of 1994 IEEE International Electron Devices Meeting ◽

10.1109/iedm.1994.383413 ◽

2002 ◽

Cited By ~ 24

Author(s):

S.H. Voldman ◽

G. Gerosa

Keyword(s):

Esd Protection ◽

Protection Circuits

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ESD Protection Circuits

Using device simulations to optimize ESD protection circuits

Design of Gate-Ground-NMOS-Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn-On

A new I/O signal latchup phenomenon in voltage tolerant ESD protection circuits

New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology

A physics-based compact model for SCR devices used in ESD protection circuits

Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits

Temperature-dependence of steady-state characteristics of SCR-type ESD protection circuits

Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits

Analysis and Measurement of Signal Distortion due to ESD Protection Circuits

Mixed-voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies

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