Influence of Nanoscale Charge Trapping Layer on the Memory and Synaptic Characteristics of a Novel Rubidium Lead Chloride Quantum Dot Based Memristor

In this study, we demonstrate solution-processed memristor devices using a CdSe/ZnS colloidal quantum dot (CQD)/poly(methyl methacrylate) (PMMA) composite and their electrical characteristics were investigated. Particularly, to obtain stable memristive characteristics with a large current switching ratio, the concentration of CdSe/ZnS QDs in the PMMA matrix was optimized. It was found that with the CdSe/ZnS QD concentration of 1 wt%, the memristor device exhibited a high current switching ratio of ~104 and a retention time over 104 s, owing to the efficient charge trapping and de-trapping during the set and reset processes, respectively. In addition, we investigated the operational stability of the device by carrying out the cyclic endurance test and it was found that the memristor device showed stable switching behavior up to 400 cycles. Furthermore, by analyzing the conduction behavior of the memristor device, we have deduced the possible mechanisms for the degradation of the switching characteristics over long switching cycles. Specifically, it was observed that the dominant conduction mechanism changed from trap-free space charge-limited current conduction to trap charge-limited current conduction, indicating the creation of additional trap states during the repeated operation, disturbing the memristive operation.

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Investigating stability and tunability of quantum dot transport in silicon MOSFETs via the application of electrical stress

Journal of Physics D Applied Physics ◽

10.1088/1361-6463/ac3da9 ◽

2021 ◽

Author(s):

Joseph Hillier ◽

Kouta Ibukuro ◽

Fayong Liu ◽

Muhammad Khaled Husain ◽

James J Byers ◽

...

Keyword(s):

Quantum Dot ◽

Coulomb Blockade ◽

Large Scale ◽

Charge Trapping ◽

Hole Transport ◽

Oxide Interface ◽

Silicon Devices ◽

Electrical Stress ◽

P Type ◽

The Impact

Abstract In this work, we experimentally investigate the impact of electrical stress on the tunability of single hole transport properties within a p-type silicon MOSFET at a temperature of T = 2 K. This is achieved by monitoring Coulomb-blockade from three disorder based quantum dots at the channel-oxide interface, which are known to lack tunability as a result of their stochastic origin. Our findings indicate that when applying gate biases between -4 V to -4.6 V, nearby charge trapping enhances Coulomb-blockade leading to a stronger quantum dot confinement that can be reversed to the initial device condition after performing a thermal cycle reset. Re-applying stress then gives rise to a predictable response from reproducible changes in the quantum dot charging characteristics with consistent charging energy increases of up to ≈ 50% being observed. We reach a threshold above gate biases of -4.6 V, where the performance and stability become reduced due to device degradation occurring as a product of large-scale trap generation. The results not only suggest stress as an effective technique to enhance and reset charging properties but also offer insight on how standard industrial silicon devices can be harnessed for single charge transport applications.

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