A placement method for size-restricted blocks in VLSI layout design

1990 ◽  
Vol 73 (9) ◽  
pp. 86-96
Author(s):  
Hiroshi Izumoto ◽  
Shin'Ichi Wakabayashi ◽  
Jun'Ichi Miyao ◽  
Noriyoshi Yoshida
Keyword(s):  
Layout Design ◽  
Vlsi Layout ◽  
Placement Method

scholarly journals An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model

VLSI Design ◽  
1994 ◽  
Vol 1 (3) ◽  
pp. 233-242 ◽  
Author(s):  
Xiaoyu Song
Keyword(s):  
Routing Algorithm ◽  
Difficult Problem ◽  
Layout Design ◽  
Channel Routing ◽  
Routing Problem ◽  
Vlsi Layout ◽  
Channel Density ◽  
Optimum Algorithm ◽  
Important Time ◽  
Optimum Channel

Channel routing problem is an important, time consuming and difficult problem in VLSI layout design. In this paper, we consider the two-terminal channel routing problem in a new routing model, called knock-knee diagonal model, where the grid consists of right and left tracks displayed at +45° and –45°. An optimum algorithm is presented, which obtains d + 1 as an upper bound to the channel width, where d is the channel density.

Hierarchical detailed floorplanning with global routing in VLSI layout design

1991 ◽  
Vol 74 (10) ◽  
pp. 85-95
Author(s):  
Michiroh Ohmura ◽  
Shin'Ichi Wakabayashi ◽  
Jun'Ichi Miyao ◽  
Noriyoshi Yoshida
Keyword(s):  
Layout Design ◽  
Global Routing ◽  
Vlsi Layout

Equidistance routing in high-speed VLSI layout design

Integration ◽  
2005 ◽  
Vol 38 (3) ◽  
pp. 439-449 ◽  
Author(s):  
Yukiko Kubo ◽  
Hiroshi Miyashita ◽  
Yoji Kajitani ◽  
Kazuyuki Tateishi
Keyword(s):  
High Speed ◽  
Layout Design ◽  
Vlsi Layout

A critical net reshape-router for high-performance VLSI layout design

2014 ◽  
Author(s):  
Yusuke Morimoto ◽  
Mitsuru Matsushita ◽  
Michiaki Muraoka ◽  
Masahiko Toyonaga
Keyword(s):  
High Performance ◽  
Layout Design ◽  
Vlsi Layout
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