scholarly journals Parallel Prefix (Scan) Algorithms for MPI

Author(s):  
Peter Sanders ◽  
Jesper Larsson Träff
Keyword(s):  
Author(s):  
K.R. Shankarkumar ◽  
Gokul Kumar

: Filtering is an important step in the field of image processing to suppress the required parts or to remove any artifacts present in it. There are different types of filters like low pass, high pass, Band pass, IIR, FIR and adaptive filtering etc.., in these filters adaptive filters is an important filter because it is used to remove the noisy signal and images. Least Mean Square filter is a type of an adaptive filtering which is used to remove the noises present in the medical images. The working of LMS is based on the minimization of the difference between the error images using a closed loop feedback. Therefore presented technique called as Q-CSKA. Here the CSKA performs its operation in stages which is based on the nucleus stage. In the traditional CSKA the nucleus stage is depend on the parallel prefix adder in this work it is replaced by the QCA adder. The QCA adder utilizes the less area compared to PPA and it can be realized in Nanometer range also. For multiplexers, And OR Invert, OR and Invert logic is used to reduce the area and delay. Due to these advantages of the QCA, AOI-OAI logic the proposed method outperformed the LMS implementation in area, power, and accuracy and delay, this based five type image noise of medical pictures related to the best technique is out comes. It helps to medicinal practitioner to resolve the symptoms of patient with ease.


2018 ◽  
Vol 7 (2.7) ◽  
pp. 647
Author(s):  
J Lakshmi Prasanna ◽  
V Sahiti ◽  
E Raghuveera ◽  
M Ravi Kumar

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs. 


2012 ◽  
Vol 43 (8) ◽  
pp. 573-581 ◽  
Author(s):  
H. Fatih Ugurdag ◽  
Onur Baskirt

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