An Efficient Implementation of Hybrid Carry Select Adder Using Parallel Prefix Addition and Binary to Excess 1 Conversion

In this paper, we propose Carry Select Adder (CSLA) architecture with parallel prefix adder. Instead of using 4-bit Brent Kung Adder (BKA), another parallel prefix adder i.e., 4-bit spanning Tree (ST) adder is used to design CSA. Because Adders are key element in digital design, which are not only performing addition operation, but also many other function such as subtraction, multiplication and division. A Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time so that we may gone for parallel prefix adders. This time critical application we use Spanning tree parallel prefix adder to drive fast results but they lead to increase in area. Proposed Carry Select Adder understands between RCA and BKA in term of area and delay. Delay of Existing adders is larger therefore we have replaced those with Brent Spanning Tree parallel prefix adder which gives fast result. This paper describes comparative performance of 4-bit RCA and 4-Bit BK parallel prefix adders with Our Proposed Spanning Tree adder based carry select adder designed using Xilinx ISE tool.

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An Efficient Implementation of Carry Select Adder with Low Power and Area Efficient Characteristics

IJARCCE ◽

10.17148/ijarcce.2014.31158 ◽

2014 ◽

pp. 8614-8617

Author(s):

BOKAM KRISHNAVENI ◽

P. SAROJA

Keyword(s):

Low Power ◽

Efficient Implementation ◽

Carry Select Adder ◽

Area Efficient

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An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic

Electronics ETF ◽

10.7251/els1721038m ◽

2017 ◽

Vol 21 (1) ◽

pp. 38

Author(s):

Shoba Mohan ◽

Nakkeeran Rangaswamy

Keyword(s):

Energy Consumption ◽

Power Consumption ◽

Clock Cycle ◽

Efficient Implementation ◽

Multiplication Operation ◽

Array Multiplier ◽

Carry Select Adder ◽

Simulation Results ◽

Array Multipliers ◽

Full Swing

In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation withi one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate and carry propagate adder. They are implemented with using full swing GDI logic. Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. The designed and existing array multipliers are simulated at 45 nm technology model and their power consumption and delay are calculated from the simulation results. It is validated that the proposed hierarchy array multiplier based on full swing GDI logic has 27% less energy consumption than the existing design. The results confirmed that implemented multiplier has shown better performance and can be used for signal and im age processing.

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